Method of forming a metal wiring in a semiconductor device

Details Method of forming a metal wiring in a semiconductor device Method of forming a metal wiring in a semiconductor device

2001-06-20

2003-09-30

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

C438S734000

Reexamination Certificate

active

06627523

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of forming a metal wiring in a semiconductor device. More particularly, the present invention relates to a method of forming a metal wiring in a semiconductor device capable of solving a poor contact with a lower wiring due to shortage of process margin in the process of forming an upper metal wiring in a higher-integration semiconductor device.
2. Description of the Prior Art
Referring now to FIGS.
1
A~
1
C, a method of forming a metal wiring in a conventional semiconductor device will be below explained.
Referring now to
FIG. 1A
, a first insulating film
12
is formed on a semiconductor substrate
11
in which a given structure is formed. After a given region of the first insulating film
12
is etched, a metal layer is formed on the etched region and is then patterned to form a lower metal wiring
13
. After forming a second insulating film
14
on the entire structure, a given region of the second insulating film
14
is etched to form a via hole through which the lower metal wiring
13
is exposed.
With respect to
FIG. 1B
, a diffusion prevention layer
15
and a seed layer
16
are sequentially formed on the entire structure including the via hole. Then, a copper layer
17
is formed by electroplating method so that the via hole can be filled.
Referring to
FIG. 1C
, the second insulating film
14
is exposed by performing CMP process, thus forming an upper metal wiring.
In case that a metal wiring is formed by means of the above process, however, the following problems occur.
First, as the integration level of semiconductor devices becomes higher, upon lithography process for forming a via hole, there necessarily occurs an alignment problem of a lower wiring and an upper wiring. Therefore, the contact area between the via hole and the wiring is reduced and the contact resistance is thus increased, which may reduce the operating speed of the device.
Second, as the via hole is formed by etching the second insulating film, when even small amount of the second insulating film is remained within the via hole, the via hole could not make an electrical connection with the lower wiring. In order to prevent this, the second insulating film is over-etched. Due to this, there is a problem that the lower wiring is damaged.
Third, as the diffusion barrier layer and the seed layer are formed, in a wiring structure of an ultra-fine structure, the space in which the copper layer can be filled within the second insulating film pattern is minimized. Thus, there is a problem that fill of the copper layer is made impossible or defects are generated, thus lowering reliability of the device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of forming a metal wiring in a semiconductor device capable of solving the problem caused by a poor contact with a lower wiring due to shortage of process margin in the process of forming an upper metal wiring in a higher-integration semiconductor device.
In order to accomplish the above object, a method of forming a metal wiring in a semiconductor device according to the present invention is characterized in that it comprises the steps of forming a seed layer on a semiconductor substrate in which given structures including a lower metal wiring are formed; forming a photosensitive film on said seed layer; patterning said photosensitive film to exposed said seed layer on the portion in which said lower metal wiring is formed; forming a metal layer on said exposed seed layer by electroplating method; removing said photosensitive film; forming a diffusion barrier layer on the entire structure including said metal layer; sequentially etching said diffusion barrier layer and said seed layer by a blanket etch process, thereby forming an upper metal wiring in which said seed layer is remained below said metal layer and a diffusion barrier layer spacer is formed on the sidewall of said metal layer; and forming an insulating film on the entire structure including said upper metal wiring, and then performing planarization process to expose a top of said upper metal wiring.


REFERENCES:
patent: 4810332 (1989-03-01), Pan
patent: 5164332 (1992-11-01), Kumar
patent: 6391771 (2002-05-01), Naik et al.

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