Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-10-13
2003-04-29
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S518000
Reexamination Certificate
active
06557020
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an information processing system and an encryption/decryption system and, in particular, to an information processing system that is capable of performing computation to any desired precision due to the hardware configuration thereof and an encryption/decryption system that is capable of performing encryptions and decryptions due to the hardware configuration thereof. In addition, the present invention also relates to an information processing system, a system LSI, and electronic equipment that use an internal or external bus line for an optical transmission method.
BACKGROUND OF ART
When complicated and large-scale computations are to be performed, such as those for random number generation, wavelet transformation, neural networks, fast Fourier transformation, and digital filters, considerations of development costs and time scales make it standard in the art to implement them by software, using general-purpose computation devices, instead of dedicated hardware which is only used in specific applications.
The recent spread of the Internet has increased the necessity of information security techniques, from the viewpoints of electronic transactions and privacy protection, and cryptographic techniques have drawn attention as effective means of providing them.
The main categories of cryptographic methods are private-key cryptosystem and public-key cryptosystem, where a typical private-key cryptosystem is the Data Encryption Standard (DES) and a typical public-key cryptosystem is Rivest-Shamir-Adleman cryptography (RSA) system.
In principle, DES is a method of rearranging or substituting of a data bit string and RSA is a method of performing residue operations on an extremely large number of bits, so a public-key cryptosystem tends to be several hundred times slower than a private-key cryptosystem. This is because public-key cryptosystems perform residue computations to an extremely high precision, using at least several hundred bits as a modulus.
In such a case, it has become common to use a cryptographic method in which a private-key cryptosystem is used to encrypt a large-volume data string and a public-key cryptosystem is used for delivering authentication, a signature, and a key, which involve a small volume of data.
With public-key cryptosystem, the encryption strength can be selected by varying the bit length of the key, so there is a demand for methods of enabling computations using public keys of various different numbers of bits that have been revealed to communications partners.
If it is desired to exceed the arithmetic precision of a general-purpose computation device, when using a technique of employing such a general-purpose computation device to implement computations by software, such as those used in random number generation, wavelet transformation, neural networks, fast Fourier transformation, and digital filters, it is necessary to support everything in the software and thus it may become impossible to implement this in reality because of increases in programming labor and processing time.
It is regulated that DES must be implemented by using hardware techniques. Therefore, it is in fact difficult to prevent third parties from breaking the ciphers of an encryption/decryption system created by software alone. If part of the encryption algorithm could be implemented by hardware, it will be possible to increase the strength of the encryption.
A single chip public-key cryptographic processor has already been proposed, similar to this public-key cryptosystem (in the proceedings of the Electronic Information Communications Society, D-I, Vol. J80-D-I, No. 8, pp. 725-735, 1997-8).
However, although this single chip public-key cryptographic processor does enable processing at any desired precision within a precision range that is set beforehand by the hardware, processing at a precision in excess of that preset precision is not possible, raising the problem that new hardware must be designed therefor.
If the computation device is configured of thin film transistors (TFTs) on a single chip, by way of example, the presence of non-operating transistors could make the entire computation device unusable, raising problems of a reduction in yield and also an increase in fabrication costs.
As yet another technical concern, recent advances in microcomputers has promoted the miniaturization and value-added capabilities of appliances in various fields, but it has become extremely difficult to design such microcomputers. Together with the push for increases integration of microcomputers formed of microprocessors (MPUs) on single chips, wiring widths are now of the submicron order and the resistance thereof is increasing, and also the stray capacities thereof have been increased by multi-layer configurations, so that distributed parameter circuits are formed in the wiring sections, which increased the propagation delays in electrical signals.
This means that it is necessary to determine the instruction cycle of the central processing unit (CPU) within the microcomputer, after considering the time required for the CPU to transmit data and addresses to other functional units and the time required before the CPU can input data from the other functional units, which increases the design load caused by signal propagation delays.
Recent trends in miniaturization and additional functions have meant that progress has been only in the directions of VLSIs and higher levels of integrations, making the design of microcomputers even more difficult.
Increases in wiring resistance and capacity have not only produced signal propagation delays, they also cause deformation of the rectangular waveforms of signals. There have been recent advances in lower power consumptions, particularly in portable electronic equipment, but if voltage levels become lower and the extent of deformation of the rectangular waveforms increases, it is no longer possible to ensure the functions of signals and erroneous operation can occur.
An objective of the present invention is to provide an information processing system that enables a system that can compute to any desired precision, using a simple hardware structure.
Another objective of the present invention is to provide an encryption/decryption system that makes it possible to facilitate the construction of a system that is required to operate at any desired precision (any desired number of bits), using hardware.
A further objective of the present invention is to provide an information processing system and an encryption/decryption system that make it possible to improve the effective yield when the system is configured on a single chip, and also improve the reliability of the system.
Yet another objective of the present invention is to provide an information processing system and a system LSI, together with electronic equipment using the same, in which signal propagation delays are reduced to a degree such that changes in signal waveform can be ignored, and which can be designed simply.
A still further objective of the present invention is to provide a system LSI, together with electronic equipment using the same, that make it possible to simplify the management of intellectual property rights when using the above encryption/decryption system in a simple manner, even when it incorporates functional blocks developed by other companies.
DISCLOSURE OF INVENTION
One aspect of the present invention relates to an information processing system in which computational processing is performed on input data in accordance with a processing sequence, for outputting data, the information processing system comprising:
a plurality of arithmetic units, each computing to an arithmetic precision of
2
m
bits (where m is, a natural number), based on the processing sequence; and
a plurality of cascade connection terminals for cascading the arithmetic units each other,
wherein, when the maximum arithmetic precision that is required during computational processing is 2
n
bits (where n is a natural number and is fixed), x numbers of (where
Amano Kazuhiko
Kasahara Hiroshi
Nakamura Tsugio
Shimoda Tatsuya
Mai Tan V.
Watson Mark P.
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