Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-06-19
2003-05-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185190, C365S185220, C365S185240, C365S185330
Reexamination Certificate
active
06567302
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices, and more particularly, to a method and apparatus for programming a memory device having multi-state cells.
BACKGROUND
Electrically erasable and programmable memory devices having arrays of what are known as multi-bit or multi-state flash cells are found in a wide variety of electrical devices. A flash cell, also called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain and a control gate over the channel region. In addition the flash cell has a floating gate between the control gate and the channel region. The floating gate is separated from the channel region by a layer of gate oxide, and an interpoly dielectric layer separates the control gate from the floating gate. Both the control gate and the floating gate are formed of doped polysilicon. The floating gate remains floating or electrically isolated. A flash cell is programmed by applying appropriate voltages to the control gate, the drain, and the source, causing electrons to pass from the channel region to the floating gate through the gate oxide. The voltage applied to the control gate, called a programming voltage, determines the amount of charge residing on the floating gate after programming, and the charge determines the voltage that must be applied to the control gate in order to allow the flash cell to conduct current between the source and the drain. This voltage is termed the threshold voltage of the flash cell, and is the physical form of the data stored in the flash cell. As charge is added to the floating gate the threshold voltage of the flash cell increases.
A multi-bit or multi-state flash cell is produced by creating multiple, distinct threshold voltage levels over a voltage range within the flash cell. Each distinct threshold voltage level corresponds to a set of data bits, with the number of bits representing the amount of data which can be stored in the multi-state flash cell. This method allows multiple bits of binary data to be stored within the same flash cell. When reading the state of the flash cell, the threshold voltage level for which the flash cell conducts current corresponds to a bit set representing data programmed into the flash cell.
A multi-state flash cell is programmed by applying a programming voltage to the control gate and holding the drain to a constant voltage over a proper time period to store enough charge in the floating gate to move the threshold voltage of the flash cell to a desired level. This threshold voltage level represents a state of the flash cell corresponding to the data stored in the flash cell. For example, a flash cell that is capable of storing four threshold voltage levels may contain two data bits, each bit having a value of “0” or “1.”
When a multi-state flash cell is programmed the programming voltage must be precise to ensure that the multi-state flash cell is accurately programmed. Multi-state flash cells are often over-programmed, or programmed with an excessive programming voltage. Accordingly, there exists a need to adequately program multi-state flash cells in memory devices and to appropriately manage over-programmed multi-state flash cells.
SUMMARY OF THE INVENTION
The above mentioned deficiencies in the conventional method of programming cells in a memory device are addressed in the following detailed description of the preferred embodiments of the invention. According to one embodiment of the invention a group of multi-state memory cells in a memory device are programmed to a first state, and then cells in a first subset of the group are programmed to a second state different from the first state.
Advantages of the invention will be apparent to one skilled in the art upon an examination of the detailed description of the preferred embodiments.
REFERENCES:
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 5043940 (1991-08-01), Harari
patent: 5142496 (1992-08-01), Van Buskirk
patent: 5153880 (1992-10-01), Owen et al.
patent: 5218570 (1993-06-01), Pascucci et al.
patent: 5293560 (1994-03-01), Harari
patent: 5321655 (1994-06-01), Iwahashi et al.
patent: 5321699 (1994-06-01), Endoh et al.
patent: 5339272 (1994-08-01), Tedrow et al.
patent: 5386388 (1995-01-01), Atwood et al.
patent: 5394362 (1995-02-01), Banks
patent: 5420822 (1995-05-01), Kato et al.
patent: 5434825 (1995-07-01), Harari
patent: 5469444 (1995-11-01), Endoh et al.
patent: 5495442 (1996-02-01), Cernea et al.
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5555204 (1996-09-01), Endoh et al.
patent: 5566125 (1996-10-01), Fazio et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5583812 (1996-12-01), Harari
patent: 5602789 (1997-02-01), Endoh et al.
patent: 5608669 (1997-03-01), Mi et al.
patent: 5608676 (1997-03-01), Medlock et al.
patent: 5621686 (1997-04-01), Alexis
patent: 5627784 (1997-05-01), Roohparvar
patent: 5638320 (1997-06-01), Wong et al.
patent: 5638326 (1997-06-01), Hollmer et al.
patent: 5642312 (1997-06-01), Harari
patent: 5648934 (1997-07-01), O'Toole
patent: 5654918 (1997-08-01), Hammick
patent: 5673224 (1997-09-01), Chevallier et al.
patent: 5684739 (1997-11-01), Takeuchi
patent: 5694366 (1997-12-01), Chevallier et al.
patent: 5729489 (1998-03-01), Fazio et al.
patent: 5737260 (1998-04-01), Takata et al.
patent: 5764568 (1998-06-01), Chevallier
patent: 5764571 (1998-06-01), Banks
patent: 5768184 (1998-06-01), Hayashi et al.
patent: 5768191 (1998-06-01), Choi et al.
patent: 5768287 (1998-06-01), Norman et al.
patent: 5771346 (1998-06-01), Norman et al.
patent: 5790453 (1998-08-01), Chevallier et al.
patent: 5903504 (1999-05-01), Chevallier et al.
patent: 5909390 (1999-06-01), Harari
patent: 5912838 (1999-06-01), Chevallier
patent: 5943260 (1999-08-01), Hirakawa
patent: 5978289 (1999-11-01), Merritt
patent: 6049899 (2000-04-01), Auclair et al.
patent: 6075738 (2000-06-01), Takano
patent: 6078518 (2000-06-01), Chevallier
patent: 6112314 (2000-08-01), Norman et al.
patent: 6163479 (2000-12-01), Chevallier
patent: 6175937 (2001-01-01), Norman et al.
patent: 6278632 (2001-08-01), Chevallier
patent: 6324094 (2001-11-01), Chevallier
Chevallier, C., “System for Performing Analog Over-Program and Under-Program Detection for a Multistate Memory Cell”, U.S. Application -S/N 09/652802 -Filed Aug. 31, 2000,.
Norman, R., et al. ,“Apparatus and Method for Detecting Over-Programming Condition in Multistate Memory Device”, U.S. Application -S/N 09/641693 -Filed Aug. 18, 2000.
Elms Richard
Micro)n Technology, Inc.
Nguyen Van Thu
LandOfFree
Method and apparatus for programming multi-state cells in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for programming multi-state cells in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for programming multi-state cells in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3019000