Method and apparatus for digital filter

Details Method and apparatus for digital filter Method and apparatus for digital filter

2000-03-27

2003-09-23

Dam, Tuan Q. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S301000

Reexamination Certificate

active

06625628

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital filter and an operation method in the digital filter, and more particularly to a cosine roll-off filter and an operation method in the filter.
2. Description of the Prior Art
Generally, a cosine roll-off filter is used to adjust a rectangular wave so as to bring its waveform into a position corresponding to a multiple of the number of taps to prevent interference due to reflection when transmitting it.
FIG. 3
shows a configuration of a conventional digital filter. In the figure, a general 5-tap FIR-type filter is shown. Specifically, multipliers M
1
to M
5
are provided corresponding to coefficients C
1
to C
5
inputted from five taps, and outputs of the multipliers M
1
to M
5
are added by adders A
1
to A
4
to obtain a final output. Input data to the filter is successively sent to subsequent stages by four flip-flops (hereinafter simply referred to as F/F)
31
to
34
.
Consider the use of the filter of
FIG. 3
in a double sampling mode. For input data of D
1
, D
2
, D
3
, . . . , D
5
, a filter output is as shown below. That is, output Y
1
by the double sampling and output Y
2
obtained one half cycle later are as follows.
 Output
Y
1
=
D
1
×(
C
5
+
C
4
)+
D
2
×(
C
3
+
C
2
)+
D
3
×
C
1
Output
Y
2
=
D
1
×
C
5
+
D
2
×(
C
4
+
C
3
)+
D
3
×(
C
2
+
C
1
)  (1)
Furthermore, when the filter is used as a cosine roll-off filter, since C
5
=C
1
and C
4
=C
2
are satisfied because of symmetry, the above expression (1) is replaced by:
Output
Y
1
=
D
1
×(
C
1
+
C
2
)+
D
2
×(
C
3
+
C
2
)+
D
3
×
C
1
Output
Y
2
=
D
1
×
C
1
+
D
2
×(
C
3
+
C
2
)+
D
3
×(
C
1
+
C
2
)  (2)
It is to be noted that the coefficients C
1
, (C
1
+C
2
), and (C
2
+C
3
) are common in both the expressions (1) and (2).
Accordingly, by sharing overlapping hardware portions in
FIG. 3
so that tap coefficients da
1
, da
2
, and da
3
are equal to C
1
+C
2
, C
2
+C
3
, and C
1
, respectively, a filter can be realized which is identical in function and about half in the number of components with respect to the FIR-type filter of the figure. The realized filter is shown in FIG.
4
.
In the figure, with multipliers M
1
to M
3
provided corresponding to coefficients da
1
to da
3
inputted from three taps, outputs of the multipliers M
1
to M
3
are temporarily stored in F/Fs
41
to
44
and are added by adders A
1
to A
4
. A final output is obtained by switching an output selector
40
.
In
FIG. 4
, an operating speed and the number of components are significantly reduced by integrating tap coefficients between oversamplings, taking advantage of the fact that input data is unchanged for the duration of oversampling in the double sampling mode.
Furthermore, with the filter, the speed of the multipliers commonly considered to have the lowest operating speed may be half that of those in
FIG. 3
, contributing to speedup.
Next, consider quadruple sampling in the filter of FIG.
5
. In
FIG. 5
, with multipliers M
1
to M
9
provided corresponding to coefficients C
1
to C
9
inputted from nine taps, outputs of the multipliers M
1
to M
9
are added by adders A
1
to A
8
to obtain a final output. Input data to the filter is successively sent to subsequent stages by four flip-flops (F/F)
51
5
o
58
.
In this case, as in the expressions (1) and (2), for input data of Dl, D
2
, D
3
, and so forth, filter output is as shown below. Specifically, output Y
1
by the quadruple sampling, output Y
2
obtained a quarter of the cycle later, output Y
3
obtained a quarter of that cycle later, and output Y
4
obtained a quarter of that cycle later satisfy the following expression.
Y
1
=
D
1
×(
C
9
+
C
8
+
C
7
+
C
6
)+
D
2
×(
C
5
+
C
4
+
C
3
+
C
2
)+
D
3
×
C
1
Y
2
=
D
1
×(
C
9
+
C
8
+
C
7
)+
D
2
×(
C
6
+
C
5
+
C
4
+
C
3
)+
D
3
×(
C
2
+
C
1
)
Y
3
=
D
1
×(
C
9
+
C
8
)+
D
2
×(
C
7
+
C
6
+
C
5
+
C
4
)+
D
3
×(
C
3
+
C
2
+
C
1
)
 
Y
4
=
D
1
×
C
9
+
D
2
×(
C
8
+
C
7
+
C
6
+
C
5
)+
D
3
×(
C
4
+
C
3
+
C
2
+
C
1
)  (3)
where if C
1
=C
9
, C
2
=C
8
, C
3
=C
7
, and C
4
=C
6
,
Y
1
=
D
1
×(
C
1
+
C
2
+
C
3
+
C
4
)+
D
2
×(
C
2
+
C
3
+
C
4
+
C
5
)+
D
3
×
C
1
Y
2
=
D
1
×(
C
1
+
C
2
+
C
3
)+
D
2
×(
C
3
+
C
4
+
C
4
+
C
5
)+
D
3
×(
C
1
+
C
2
)
Y
3
=
D
1
×(
C
1
+
C
2
)+
D
2
×(
C
3
+
C
4
+
C
4
+
C
5
)+
D
3
×(
C
1
+
C
2
+
C
3
)
Y
4
=
D
1
×
C
1
+
D
2
×(
C
2
+
C
3
+
C
4
+
C
5
)+
D
3
×(
C
1
+
C
2
+
C
3
+
C
4
)  (4)
Accordingly, as in
FIG. 4
, an FIR-type filter of
FIG. 6
can be obtained by sharing overlapping hardware portions in FIG.
5
.
Tap coefficients ka
1
, ka
2
, ka
3
, kb
1
, kb
2
, and kb
3
are equal to C
1
+C
2
+C
3
+C
4
, C
2
+C
3
+C
4
+C
5
, C
1
, C
1
+C
2
+C
3
, C
3
+C
4
+C
4
+C
5
, and C
1
+C
2
, respectively.
In the figure, with multipliers M
11
to M
13
provided corresponding to coefficients ka
1
to ka
3
inputted from three taps, outputs of the multipliers M
11
to M
13
are temporarily stored in F/Fs
611
to
614
and are added by adders A
11
to A
14
.
A counterpart of the same configuration described above is provided (portion indicated by dashed lines in the figure). Specifically, with multipliers M
21
to M
23
provided corresponding to coefficients kb
1
to kb
3
inputted from three taps, outputs of the multipliers M
21
to M
23
are temporarily stored in F/Fs
621
to
624
and are added by adders A
21
to A
24
. A final output is obtained by switching an output selector
60
.
In the example of
FIG. 6
, in 2N-times (N is a positive integer) sampling operations such as quadruple or octuple sampling, a filter can be realized which is half in the number of components and ½N in multiplier operating speed with respect to normal FIR-type filters.
As described above, the prior art is described in, e.g., Japanese Published Unexamined Patent Application No. Hei 5-55875. Such a digital filter is very efficiently configured. However, to realize, e.g., a 113-tap octuple-sampling filter would require 60 multipliers and 112 adders. An example of configuration in this case is shown in FIG.
7
. In the figure, a number of multipliers, adders, and F/Fs (a block indicated by a rectangle in
FIG. 7
) are provided corresponding to incoming coefficients fa
1
to faF and fb
1
to fbF, and further, a counterpart of the same configuration is provided. Therefore, there is a drawback in that a huge amount of hardware is required. Concrete expressions of the coefficients fa
1
to faF and fb
1
to fbF are omitted.
There is also a problem that the operating speed of a filter depends on the switching speed of a selector at the last output stage. Specifically, the operating speed of an entire filter is determined by the operating speed of the selectors
40
,
60
, and the like of the last output stage, making it difficult to increase an operating speed.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described drawbacks of the prior art, and its object is to offer a digital filter that has a small amount of hardware and a high operating speed, and an operation method in the digital filter.
A digital filter according to the present invention is a digital filter including multiplying means for multiplying input data and predetermined coefficients and adding means for

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