Pulse or digital communications – Transmitters
Reexamination Certificate
1999-12-31
2003-05-27
Pham, Chi (Department: 2631)
Pulse or digital communications
Transmitters
C327S108000, C327S261000, C327S276000
Reexamination Certificate
active
06570931
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to switched voltage adaptive slew rate control and a spectrum shaping transmitter for, among other possible uses, high speed digital transmission.
BACKGROUND
Current mode transmitters, as shown in
FIG. 1
, with high noise immunity and lower switching noise, are widely used for high-speed digital data transmission. However, current mode transmitters usually require stack or saturation transistors for high accuracy current generation, which imposes a limit on the lowest applicable operation voltage of the transmitter. Alternatively, a voltage mode transmitter, as shown in
FIG. 2
, may be used to lower this operation voltage limit.
There are several design concerns associated with most voltage mode transmitters. First, transmitter power supply design specifications will be tighter, because unlike the current mode transmitter, the voltage mode transmitter itself does not provide the voltage or current regulating capability. Therefore, power supply noise coupling to the signal may be significant which may degrade the transmitted signal performance.
Second, the transmitter output impedance uncertainty during switching may cause significant impedance mismatch and result in unexpected reflections. As line speeds and lengths increase, the problem of signal reflections becomes important. It should be noted that there will be no reflection at the termination only when the terminating impedance (R as represented in
FIG. 3
) is equal to the characteristic impedance (Zo as represented in
FIG. 3
) of the line. Thus, a terminating impedance different from Zo will give rise to a reflected wave which travels away from the termination. The reflection, upon reaching the other end, will itself be reflected if the terminating impedance at that end is different from Zo.
Third, the high sensitivity of output signal slew rate to the device parasitic, power supply, temperature, and process variations may make the electromagnetic interference (EMI), reflection, and other undesired effects by slew rate control ineffective. As shown in
FIG. 4
, the signal at point C is delayed because of capacitors and connectors in the line which are responsible for refraction and noise. High speed digital data transmission systems usually suffer from reflections generated by discontinuities on the signal path at the package, connectors, board, and cable interfaces. These reflections can significantly affect the input/output timing margins and degrade system performance. Fly time (tf), for example, which represents the delay of signal C with respect to signal A, is generally due to cable propagation delay.
Fourth, large switch transistors switching DC paths may generate high power supply switching noises (di/dt, IR, etc.).
In addition to impedance matching, the minimization of these reflections usually requires the slew rate of the transmitted data signal to be well controlled. But a problem arises with wide process, voltage, and temperature variations. It is observed that an optimal slew rate at one process corner can result in four or five times difference from the optimal value at a different corner. The excessively slow or fast slew rate in turn results in large data jitter and degrades system performance. Therefore in high speed data transmission, an effective slew rate control scheme is very important.
Traditionally, external resistors and capacitors were used in order to match impedance and control the slew rate. Because adjusting resistors and capacitors is extremely difficult and also not cost-effective, a new technique is needed.
SUMMARY
In accordance with the invention, there is disclosed an apparatus including a switched voltage bit cell (SVBC) array to receive an input voltage signal, each bit cell of the SVBC array configured to add a voltage to the input voltage signal and a delay locked-loop configured to delay an output voltage signal of each bit cell of the SVBC array by a determined step.
REFERENCES:
patent: 4988960 (1991-01-01), Tomisawa
patent: 5245231 (1993-09-01), Kocis et al.
patent: 5272453 (1993-12-01), Traynor et al.
patent: 5559476 (1996-09-01), Zhang et al.
patent: 5898326 (1999-04-01), Okayasu
patent: 5977819 (1999-11-01), Sanwo et al.
patent: 6166572 (2000-12-01), Yamaoka
patent: 6490325 (2002-12-01), Fiedler et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Pham Chi
Tran Khanh Cong
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