Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – For fault location
Reexamination Certificate
2001-02-06
2003-07-29
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
For fault location
C324S686000, C324S690000, C324S758010, C324S555000
Reexamination Certificate
active
06600325
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the testing of integrated circuits. More specifically, the present invention relates to a method and an apparatus for probing electrical signals within an integrated circuit using a capacitive mechanism that requires no physical contact with the integrated circuit.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems into a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, integrating a large-scale system onto a single semiconductor chip can greatly complicate the task of testing. This testing is presently performed in a number of ways. An automated system of probing can be performed by using a probe card and a test system. This probe card makes electrical contact to the pads normally used to communicate to the chip. After a wafer is cut into individual die and assembled, it can be tested again using similar techniques.
Note that probe points are typically very large in comparison to feature size. Moreover, probing is normally limited to only the pins that will be the external inputs and outputs of the final semiconductor chip. Furthermore, additional probe pads can be added to monitor other critical signals to help determine which die are functional. Unfortunately, these extra probe points consume valuable chip area because they must follow the same tolerance/size area of normal pads.
Furthermore, many important signals are weak and therefore must be amplified to drive the probe pads. This amplification process requires additional circuitry and introduces additional delay.
Functional testing can also be performed using built-in scan-path structures at the same time wafer probing is taking place or after a die is packaged into a chip. However, scan-path testing can be prohibitively slow because of the large amount of data that is typically required to be scanned on and off chip. Furthermore, the scan testing clock is often significantly slower than the actual system clock.
What is needed is a method and an apparatus for testing an integrated circuit without the problems associated with large probe points and without the performance problems associated with using scan-path structures.
SUMMARY
One embodiment of the present invention provides a system for capacitively probing electrical signals within an integrated circuit. This system operates by placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit. In this position, the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor. Next, the system detects a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor, and then determines a logic value for the target conductor based on the change in the probe voltage.
In one embodiment of the present invention, determining the logic value for the target conductor involves, determining a first value if the probe voltage decreases, and determining a second value if the probe voltage increases.
In one embodiment of the present invention, the target conductor is located in a highest metal layer of the integrated circuit.
In one embodiment of the present invention, placing the probe conductor in close proximity to the target conductor involves aligning the probe conductor with the target conductor using an electrical, mechanical or optical alignment mechanism.
In one embodiment of the present invention, the present invention causes a liquid dielectric to be placed between the probe conductor and a target conductor.
In one embodiment of the present invention, the system additionally allows the logic value to be gathered by testing circuitry coupled to the probe conductor.
In one embodiment of the present invention, the probe conductor is located on a second integrated circuit. In this embodiment, the target conductor is used to drive a value onto the second integrated circuit through the probe conductor.
In one embodiment of the present invention, the target conductor includes a plurality of target conductors disposed on a surface of the integrated circuit. Furthermore, the probe conductor includes a plurality of probe conductors disposed on a surface of a second integrated circuit. This allows the plurality of probe conductors to simultaneously monitor the plurality of target conductors when the plurality of probe conductors are aligned with the plurality of target conductors. In a variation on this embodiment, the plurality of probe conductors are organized into a two-dimensional grid on the second integrated circuit. In a variation on this embodiment, during design of the integrated circuit, a plurality of target signals from within the integrated circuit are routed to the plurality of target conductors. This allows the plurality of target signals to be monitored by the plurality of probe conductors. In a variation on this embodiment, the target conductor includes a bonding pad of the integrated circuit.
REFERENCES:
patent: 4392378 (1983-07-01), Pitches et al.
patent: 5124660 (1992-06-01), Cilingiroglu
patent: 5157325 (1992-10-01), Murphy
patent: 5274336 (1993-12-01), Crook et al.
patent: 5469064 (1995-11-01), Kerschner et al.
patent: 5629838 (1997-05-01), Knight et al.
Bosnyak Robert J.
Coates William S.
Sutherland Ivan E.
Le N.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
Teresinski John
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