Semiconductor memory device having sensing power driver

Details Semiconductor memory device having sensing power driver Semiconductor memory device having sensing power driver

2001-12-28

2003-03-11

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S207000

Reexamination Certificate

active

06532186

ABSTRACT:

BACKGROUND
1. Technical Field
The present invention relates to semiconductor memory devices, and in particular to semiconductor memory devices and sense amplifier control circuits thereof that can improve power serviceability of sensing power drivers, as well as improve sensing speed of bit line sense amplifiers by selectively connecting at least two sensing power drivers of one block to common sensing power lines.
2. Description of the Background Art
In general, methods for supplying sensing power RTO and /S to a sense amplifier may be classified as a method for driving a word line using a metal strap or a method for driving a word line using a sub-word line.
The former method was suggested in early development stages of semiconductor memory devices. Here, the sensing power is coupled to a sense amplifier outside a cell array block according to a block select address. In this method, power serviceability is decided according to a magnitude of the sensing power RTO and /S existing outside a memory cell array. According to this method, one sensing power RTO and /S exists in a block controlled according to the block select address.
The latter method has been more recently used. Here, sensing power drivers are aligned in sub-holes formed in the regions where sub-word line array regions and a sense amplifier array block cross one another between memory cell array blocks, and the sensing power RTO and /S is controlled according to sensing power supply control signals RTOEN and /SEN including a block address.
FIG. 1
is a block diagram illustrating a conventional semiconductor memory device for supplying the sensing power RTO and /S of a bit line sense amplifier to a bit line sense amplifier array block.
Referring to
FIG. 1
, a plurality of memory cell array blocks
1
are aligned in one bank in a matrix-type configuration. Bit line sense amplifier array blocks
2
a
and
2
b
are connected to both side ends of the memory cell array blocks
1
. Sensing power drivers
3
a,
3
b,
3
c
and
3
d
for supplying the sensing power RTO and /S to the bit line sense amplifier array blocks
2
a
and
2
b
are aligned in each sub-hole. Sensing power supply control signal lines RTOEN
0
and /SEN
0
, which supply sensing power supply control signals RTOEN and /SEN for controlling the sensing power drivers
3
a,
3
b,
3
c
and
3
d,
are aligned between the memory cell array blocks
1
. Sensing power lines RTO
0
and /S
0
that supply the sensing power RTO and /S are driven according to the sensing power drivers
3
a,
3
b,
3
c
and
3
d
and are coupled to the bit line sense amplifier array blocks
2
a
and
2
b
are positioned between the sensing power supply control signal lines RTOEN
0
and /SEN
0
.
As illustrated in
FIG. 2
, the sensing power driver
3
a
includes NMOS transistors NM
1
-NM
3
controlled according to a bit line precharge control signal BLP, for precharging and equalizing the sensing power lines RTO
0
and /S
0
to a precharge voltage VBLP and a PMOS transistor PM
1
controlled according to the sensing power supply control signal RTOEN
0
, for selectively transmitting an external power voltage VEXT to the sensing power line RTO
0
. The sensing power driver
3
a
also includes an NMOS transistor NM
4
controlled according to the sensing power supply control signal /SEN
0
, to selectively connect the sensing power line /S
0
to a ground.
The operation of the conventional sensing power driving circuit of the bit line sense amplifier are now explained.
The sensing power drivers
3
a,
3
b,
3
c
and
3
d
are aligned in the sub-holes formed in the regions where sub-word line array regions
4
a
and
4
b
and the sense amplifier array blocks
2
a
and
2
b
cross one another. The sensing power drivers
3
a,
3
b,
3
c
and
3
d
are controlled according to the sensing power supply control signals RTOEN
0
, RTOEN
1
, /SEN
0
and /SEN
1
.
For example, when an i-th word line WLi of the memory cell array block
1
of
FIG. 1
is selected, the bit line sense amplifier array blocks
2
a
and
2
b,
which are positioned at both side ends of the memory cell array block
1
, sense and amplify data in a read or write operation. Here, the sensing powers RTO
0
, /S
0
, RTO
1
and /S
1
of the bit line sense amplifier array blocks
2
a
and
2
b
for reading or writing data of the selected memory cell array block
1
are respectively controlled according to the sensing power supply control signals RTOEN
0
, /SEN
0
, RTOEN
1
and /SEN
1
. That is, when the i-th word line WLi is enabled, the sensing power supply control signals RTOEN
0
, /SEN
0
, RTOEN
1
and /SEN
1
are enabled according to the block select address.
When the sensing power supply control signals RTOEN
0
, /SEN
0
, RTOEN
1
and /SEN
1
are enabled, the PMOS transistor PM
1
and the NMOS transistor NM
4
are turned on according to the arrangement of
FIG. 2
, thereby supplying the external power voltage VEXT and the ground voltage VSS to the sensing power lines RTO
0
and /S
0
, respectively.
Because the NMOS transistors NM
1
-NM
3
have been already turned on according to the bit line precharge control signal BLP, the sensing power lines RTO
0
and /S
0
were precharged to the precharge voltage VBLP.
Therefore, the sensing lines RTO and /S are aligned in the sub-holes, and driven by the sensing power driver
3
a
controlled according to the sensing power supply control signals RTOEN
0
, /SEN
0
, RTOEN
1
and /SEN
1
. As a result, when a sub-hole area is decreased due to reduction of the sense amplifier array blocks and the sub-word line regions according to high integration of the semiconductor memory device, a size of the sensing power drivers is also reduced, which results in low driving capacity.
SUMMARY
According to one aspect, the disclosed device may be a semiconductor memory device that may include a plurality of memory cell array blocks aligned in a matrix-type configuration and a plurality of sense amplifier array blocks for sensing and amplifying data stored in the respective memory cell array blocks. The disclosed device may also include a plurality of sensing power drivers for supplying sensing power to the respective sense amplifier array blocks according to sensing power supply control signals and a plurality of switches for commonly connecting output terminals of at least two sensing power drivers to common sensing power lines according to the sensing power supply control signals.
In such an arrangement, the sensing power supply control signals may be generated using block select address signals. Additionally, the switches may be formed in sub-holes.


REFERENCES:
patent: 5272677 (1993-12-01), Yamamura
patent: 5280450 (1994-01-01), Nakagome et al.
patent: 5495454 (1996-02-01), Fukuzo
patent: 5650972 (1997-07-01), Tomishima et al.
patent: 5671188 (1997-09-01), Patel et al.
patent: 5822262 (1998-10-01), Hashimoto et al.
patent: 5966341 (1999-10-01), Takahashi et al.
patent: 6392951 (2002-05-01), Fujima et al.
U.K. Search Report dated Jul. 31, 2002.

Affiliated with

Also associated with

Rating

Semiconductor memory device having sensing power driver does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having sensing power driver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having sensing power driver will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3016817