Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2002-03-26
2003-09-30
Mai, Son (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C361S777000, C361S778000, C361S803000
Reexamination Certificate
active
06628538
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology capable of controlling the reflection of a transmission signal, which is caused by branch wirings (stub) in a memory module, and to a technology effective for application to a high-speed access-compatible memory module.
SSTL (Stub Series Terminated Transceiver Logic) has been known as a small-amplitude interface intended for a memory module. The SSTL has been described in, for example, English Paper Journal, VOL. E82-C, NO. 3, Yasuhiro KONISHI, et al., “Interface technologies for Memories and ASICs-Review and Future Direction”, issued by the Institute of Electronics, Information and Communication Engineers, March 1999.
A memory system using SSTL principally comprises a memory controller, signal wirings, connectors and memory modules mounted on a motherboard. The memory modules respectively have m memory chips provided on both surfaces of a module substrate. Data terminals of each individual memory chips are connected to their corresponding module data terminals in m units. Access control data terminals such as address terminals of the memory chips are connected to their corresponding module access control terminals. One-sided ends of the signal wirings are connected to their corresponding signal terminals of the memory controller, and the other ends thereof are terminated into a predetermined voltage. A plurality of memory modules are connected in parallel with their corresponding signal wirings through the connectors. Assuming now that the number of data terminals of each memory chip is defined as n and the number of the memory chips placed on the one side of each memory module is defined as m, the present memory system has m×n data signal wirings. The m memory chips placed on the one side of one memory module of plural memory modules are selected for one access according to a chip select signal generated by the memory controller. The ends or terminals of the signal wirings are connected to a terminal voltage through terminating resistors. Stub resistors for the memory controller are respectively series-connected to signal wirings for connecting the memory controller and the connectors.
Here, module wirings for connecting the module terminals of each memory module and the terminals of each memory chip constitute wirings which branch off from the signal wirings of the motherboard through the connectors. Stub resistors are placed in these module wirings. These stub resistors serve as matching loads for relaxing signal reflection developed in the signal wirings. Mismatching is generally developed in characteristic impedance at each wiring branch point. It is thus necessary to provide the stub resistors for relaxing the mismatching. Assuming that the characteristic impedance of each wiring is defined as Z
0
and the characteristic impedance of each stub wiring is defined as Zs
0
, Zs—Z
0
/2 is suitable as the resistance value of each stub resistor. There is however the possibility that when the resistance value of the stub resistor increases, a voltage drop developed across the resistor will become great, thereby attenuating signal voltages such as addresses, data or the like and hence causing an error in a memory operation. When the resistance value of the stub resistor is less reduced to avoid the attenuation of the signal voltage for this season, there is the possible that signal reflection will become obvious in reverse and hence a signal waveform will disturb, thereby causing a malfunction in the same manner as described above. As the operation is made fast to increase a signal frequency and each branch wiring against which countermeasures are to be taken by the stub resistor, becomes long, the disturbance of a signal waveform at a receiving end becomes great.
On the other hand, the present inventors have discussed, as another memory system, a type wherein a plurality of memory modules are series-connected via connectors to their corresponding signal wirings connected to a memory controller on a motherboard. The present inventors have discussed a configuration wherein on a memory module, a plurality of memory chips are connected by one-stroke writable wiring paths through data signal wirings. Assuming that the number of data signal terminals of each memory element is defined as n in the present memory system, n module data signal wirings are provided therein regardless of the number m of memory elements placed on one side of each memory module, and one memory chip of the plural memory chips is selected for one access.
In another memory system referred above, all the memory modules are series-connected to their corresponding signal wirings of the motherboard, and the module signal wirings lying within the memory modules are series-connected to all the memory chips arranged in a line and are laid along the longitudinal direction of each memory module. Thus, a problem decreases that as in the case of the SSTL, the memory modules little form the branch wirings with respect to the signal wirings on the motherboard, and the disturbance of each waveform due to undesired signal reflection caused by the branch wirings occurs.
However, the present inventors have revealed that the length of the signal wiring increases, and the time necessary for the signal to propagate from the memory controller to the corresponding memory chip at the farthest end thereof becomes long, thus increasing a delay in access time.
Thus, a problem arises in that the module wirings of each memory module constitute the branch wirings on the memory system in the case of the SSTL type, whereby the malfunction due to the signal reflection caused thereby occurs and the speeding up of the memory operation is limited. Since such branching for the signal wiring as developed in the SSTL little exists in the memory module of such a type that the memory chips are connected in series, the branch wiring-based problem decreases. However, the present inventors have revealed the possibility that an increase in the length of the signal wiring lying within each memory module will cause a delay in access time and cannot cope with higher-speed access.
After the completion of the invention of the present application, the inventors of the present application have recognized the following examples known to date. Japanese Patent Application Laid-Open Nos. Hei 5(1993)-234355 and 6(1994)-150085 respectively have disclosed the invention wherein connectors are provided at both long-side portions of each memory module so that the plural memory modules can be connected in tandem. However, they do not disclose a wiring structure provided inside each memory module. Japanese Patent Application Laid-Open No. Hei 7(1995)-334415 discloses a memory module having extended connectors which allow cascade connections of extended memory modules. Japanese Patent Application Laid-Open No. Hei 7(1995)-261892 discloses the invention wherein each of memory modules is provided with inlet connectors and outlet connectors, a memory bus on the memory module connects between them, and memory elements are connected in series with the memory bus, whereby undesired signal reflection is controlled. However, the first through third known examples merely provide the technology of the cascade-connectable memory modules. The fourth known example merely shows the system for connecting the plural memory elements to their corresponding memory bus on each memory module in series form. Any of the examples does not provide the conception leading to the invention of the present application.
SUMMARY OF THE INVENTION
The present invention aims to provide a memory module capable of controlling the disturbance of a signal waveform due to signal reflection to improve the reliability of signal transmission and restraining an increase in access time.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will
Funaba Seiji
Horiguchi Masashi
Nakagome Yoshinobu
Nishio Yoji
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Mai Son
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