Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-03-29
2003-09-16
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06621285
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip and to a method for testing operation of such a semiconductor chip. More particularly, the present invention discloses a semiconductor chip provided with a plurality of pads for input and output of signals, and a method for testing operation state of a plurality of semiconductor chips arranged in a matrix on a wafer.
2. Description of the Related Art
Integrated circuits (ICs) are mass-produced in the following manner. A wafer provided with a plurality of semiconductor chips arranged in a matrix is diced into individual semiconductor chips. After each of the thus divided semiconductor chips is mounted to a package, pads of the semiconductor chip used for input and output of signals are connected with bonding wires to an island of the package formed of copper, iron, or the like. A semiconductor chip thus connected to the package by means of bonding wires is molded with protective resin, thereby forming an IC. Defective ICs among those produced must be separated before the ICs are delivered to customers. Therefore, before dicing the wafer into individual semiconductor chips, the chips are tested using a tester to identify defective chips, which are removed before being shipped to a customer. Such testing is usually performed with a tester by bringing the signal input/output (I/O) pads of the chip into contact with a probe mounted to the tester and commonly formed of tungsten or the like, and supplying a signal, such as a control signal, to the signal I/O pads from the probe under the control of the tester to detect operation state of the semiconductor chip. When the semiconductor chip does not operate as expected, the chip is determined to be defective.
Semiconductor chips can be roughly divided into multi-pin semiconductor chips having a relatively large number of pins, and those representing a fewer pin type.
FIG. 3
is a plan view illustrating a conventional multi-pin type semiconductor chip
200
. On the chip
200
, 25 pads are disposed along each of its four sides. More specifically, on the multi-pin type semiconductor chip
200
, pads
1
-
25
are arranged on one side, pads
26
-
50
on an adjacent side, pads
51
-
75
on the next side, and pads
76
-
100
on the remaining side. When the multi-pin type semiconductor chip
200
is a one-chip microcomputer, verification may sometimes be required as to whether or not data stored in a ROM is correct. When a ROM has a storage capacity of, for example, 64 kB, 28 pads are required to verify operation of the ROM, namely,
16
pads for supplying address data, 8 pads for reading and writing data, and 4 pads for controlling the ROM.
FIG. 4
is a plan view illustrating a plurality of multi-pin semiconductor chips
200
having these 28 pads on the opposing two sides, each contacted by the probe of the tester. An arrow in the figure indicates the position of the probe. While 25 pads are arranged along each of the four sides of the multi-pin type semiconductor device
200
, some of the pads on the opposing two sides, i.e. pads
1
-
25
and
51
-
75
, serve as the above 28 pads. By thus arranging pads for verifying operation of the ROM on the opposing two sides, a plurality of multi-pin type semiconductor chips can be simultaneously brought into contact with the probes of the tester, achieving simultaneous testing of a plurality of multi-pin type semiconductor chips.
FIG. 5
is a plan view illustrating a conventional fewer pin type semiconductor chip
300
, where 7 pads are arranged on each of four sides. More specifically, on the semiconductor chip
300
, pads
1
-
7
are arranged on one side, pads
8
-
15
on an adjacent side, pads
16
-
22
on the next side, and pads
23
-
30
on the remaining side. When the semiconductor chip
300
is a one-chip microcomputer and the ROM has a storage capacity of 1 kB, 22 pads are required for verifying operation state of the ROM, namely, 10 pads for supplying address data, 8 pads for reading and writing data, and 4 pads for controlling the ROM.
However, it is impossible, on a fewer pin type semiconductor chip, to arrange 22 pads on just two opposing sides for verifying operation of the ROM, and therefore the pads must be arranged on all four sides.
FIG. 6
is a plan view illustrating a plurality of fewer pin type semiconductor chips
400
provided with 22 pads on four sides, and the probe of the tester contacts each of the pads. An arrow in the figure indicates the position of the probe.
As can be seen from
FIG. 6
, the probe of the tester cannot contact a portion
410
where two chips adjoin, and simultaneous testing of a plurality of fewer pin type semiconductor chips is therefore impossible. In other words, the chips must be tested one at a time, resulting in longer testing times and higher costs.
Further, the size of the package and arrangement of the island therein is determined according to the number of pads on the semiconductor chip. Consequently, if the number of pads provided on the opposing sides of the chip
400
is increased, arrangement of the island must be changed, which increases the cost of the resulting chip. If rearrangement of the island is made by connecting bonding wires in an unspecified manner, a short circuit may be caused between adjacent wires, which again increases final product cost as the short circuited chip must be discarded.
SUMMARY OF THE INVENTION
The present invention aims to provide a semiconductor chip with a pad arrangement that enables simultaneous testing of a plurality of semiconductor chips, and a testing method for simultaneously testing a plurality of semiconductor chips.
According to one aspect of the present invention, a semiconductor chip includes a signal input/output pad disposed at a peripheral region for inputting/outputting a signal to/from a semiconductor device, and a measurement pad disposed on a side other than the side where the signal input/output pad is arranged, and electrically connected to the signal input/output pad.
In the above semiconductor chip, the semiconductor device may be a memory.
According to another aspect of the present invention, a semiconductor chip includes a plurality of signal input/output pads disposed along four sides for inputting/outputting a signal to/from a semiconductor device, and a measurement pad arranged along two opposing sides among the four sides, and electrically connected to the plurality of signal input/output pads arranged on the two remaining opposing sides.
In the above semiconductor chip, the semiconductor device may be a memory.
According to still another aspect of the present invention, a method for testing operation of a semiconductor chip relates to a method for testing operation state of a plurality of semiconductor chips arranged on a wafer in a matrix, and each of the semiconductor chips includes a signal input/output pad arranged at a peripheral region for inputting/outputting a signal to/from a semiconductor device, and a measurement pad arranged on a side other than the side where the signal input/output pad is arranged, and electrically connected to the signal input/output pad. The above method includes the steps of:
(a) inputting/outputting a signal to/from the semiconductor device of the semiconductor chip using the measurement pad, and
(b) determining the operation state of the semiconductor chip based on an output of the signal.
In the above method for testing operation of a semiconductor chip, the semiconductor device may be a memory, and step (b) may include a step of detecting content written in the memory.
According to a further aspect of the present invention, the method for testing operation of a semiconductor chip relates to a method for testing operation state of a plurality of semiconductor chips arranged in a matrix on a wafer, and each of the semiconductor chips includes a plurality of signal input/output pads arranged along four sides for inputting/outputting a signal to/from a semiconductor device, and a measurement pad arranged along two opposing sides among
Cantor & Colburn LLP
Nguyen Vinh P.
Sanyo Electric Co,. Ltd.
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