Solid state image pickup device and its manufacture

Details Solid state image pickup device and its manufacture Solid state image pickup device and its manufacture

2000-08-04

2003-01-14

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S232000, C257S233000, C257S241000

Reexamination Certificate

active

06507055

ABSTRACT:

This application is based on Japanese Patent Application HEI 11-227768, filed on Aug. 11, 1999, and 2000-213600 filed on Jul. 14, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a CCD solid state image pickup device and its manufacture, and more particularly to improvements on a transfer efficiency of electric charges of a solid state image pickup device to be transferred from vertical charge transfer paths to a horizontal charge transfer path.
b) Description of the Related Art
The structure of a general interline CCD solid state image pickup device will be described with reference to
FIG. 13
,
FIGS. 14A and 14B
, and
FIGS. 15A and 15B
.
FIG. 13
is a plan view of a general interline CCD solid state image pickup device, and
FIGS. 14A and 14B
are schematic cross sectional views illustrating charge transfer in a vertical charge transfer path VCCD and a horizontal charge transfer path HCCD.
FIG. 14A
shows the structure of the vertical charge transfer path VCCD, and
FIG. 14B
shows the structure of the horizontal charge transfer path HCCD.
FIG. 15A
is a schematic cross sectional view showing the structure of a region including a vertical charge transfer channel layer, and
FIG. 15B
is a schematic cross sectional view showing the structure of a horizontal charge transfer channel layer.
A solid state image pickup device A is formed, for example, in an n-type semiconductor layer
101
formed on a semiconductor substrate of silicon or the like.
In this n-type semiconductor layer
101
, pixels
103
, vertical charge transfer paths
105
, a horizontal charge transfer path
107
and an output amplifier
111
are formed. A plurality of pixels
103
are formed on this n-type semiconductor layer
101
, regularly disposed in vertical and horizontal directions.
Each pixel
103
includes a photodiode (photoelectric conversion element)
103
a
and a transfer gate
103
b.
The photodiode
103
a
converts received light into electric charges and stores the electric charges.
The transfer gate
103
b
is a read gate which is used when electric charges stored in the photodiode
103
a
are read.
Along each pixel column with a plurality of pixels
103
being regularly disposed in the vertical direction, one vertical charge transfer channel region
105
is disposed which is made of, for example, an n-type semiconductor layer.
Along the lower ends of a plurality of vertical charge transfer channel layers
105
, a horizontal charge transfer channel layer
107
is disposed which is made of, for example, an n-type semiconductor layer.
A p-type semiconductor layer
108
is formed surrounding the vertical charge transfer layers
105
and horizontal charge transfer channel layer
107
.
As shown in
FIG. 14A
, the p-type semiconductor layer
108
is formed on one surface of the n-type semiconductor layer
101
. The vertical charge transfer channel layer
105
is formed in this p-type semiconductor layer
108
. The vertical charge transfer channel layer
105
is made of a semiconductor layer having generally a uniform n-type (first conductivity type) impurity concentration.
Two charge transfer electrodes
121
per one pixel row are formed on the vertical charge transfer channel layer
105
. Voltages &PHgr;
1
to &PHgr;
4
are applied to adjacent four charge transfer electrodes
121
.
The vertical charge transfer path VCCD is constituted of the vertical charge transfer channel layer
105
and charge transfer electrodes
121
. Four-phase drive voltages V
1
to V
4
are applied to four vertical transfer electrodes adjacent in the vertical direction. With this four-phase driving, charges in the vertical charge transfer channel layer
105
are transferred toward the horizontal charge transfer channel layer
107
.
As shown in
FIG. 14B
, the p-type semiconductor layer
108
continuous with the p-type semiconductor layer
108
shown in
FIG. 14A
is formed on one surface of the n-type semiconductor layer
101
. The horizontal charge transfer channel layer
107
is formed in the p-type semiconductor layer
108
. The horizontal charge transfer channel layer
107
is formed by disposing first and second horizontal charge transfer channel layers
107
-
1
and
107
-
2
having different n-type (first conductivity type) concentrations. The n-type impurity concentration of the first horizontal charge transfer channel layer
107
-
1
is higher than that of the second horizontal charge transfer channel layer
107
-
2
. Alternatively, the second horizontal charge transfer channel layer
107
-
2
may be doped with first conductivity type impurities having the same concentration as the first horizontal charge transfer channel layer
107
-
1
and with impurities of a second conductivity type opposite to the first conductivity type. By doping the impurities of the opposite conductivity type, the effective first conductivity type impurity concentration is lowered. A potential profile of a two-stage structure having a potential barrier on the right side is repetitively formed from right to left in FIG.
14
B. Two potential structures each having a potential barrier and a potential well are disposed in the horizontal direction to constitute one unit of charge transfer (hereinafter called “one packet”).
A plurality of charge transfer electrodes
123
are formed on the horizontal charge transfer channel layer
107
in position alignment with the first and second horizontal charge transfer channel layers
107
-
1
and
107
-
2
. A first transfer electrode
123
-
1
made of first layer polysilicon and a second transfer electrode
123
-
2
made of second layer polysilicon are alternately disposed side by side in the horizontal direction.
For example, the first transfer electrode
123
-
1
is formed on the first horizontal charge transfer channel layer
107
-
1
, and the second transfer electrode
123
-
2
is formed on the second horizontal charge transfer channel layer
107
-
2
.
Adjacent two charge transfer electrodes
123
-
1
and
123
-
2
are connected in common, and the next adjacent two charge transfer electrodes
123
-
1
and
123
-
2
are also connected in common. Voltages &PHgr;
1
and &PHgr;
2
are alternately applied to these common connections. This structure is repeated in the horizontal direction. With two-phase driving of &PHgr;
1
and &PHgr;
2
, charges in the horizontal charge transfer channel layer
107
are transferred left in the horizontal direction.
The vertical charge transfer channel layers
105
are electrically connected to every second first horizontal charge transfer channel layers (potential well)
107
-
1
formed in the horizontal charge transfer channel layer
107
.
As shown in
FIG. 15A
, the p-type semiconductor layer
108
is formed in the n-type semiconductor layer
101
. The vertical charge transfer channel layer
105
is formed in the p-type semiconductor layer
108
.
As shown in
FIG. 15B
, the p-type semiconductor layer
108
is formed in the n-type semiconductor layer
101
. The horizontal charge transfer channel layer
107
is formed in the p-type semiconductor layer
108
.
In
FIG. 13
, the p-type semiconductor layers
108
are indicated by one-dot chain lines. The p-type semiconductor layers
108
are formed in areas including the vertical charge transfer channel layers
105
and horizontal charge transfer channel layer
107
by using the same process and have the same depth and impurity concentration.
The cross section of the first horizontal charge transfer channel layer
107
-
1
having generally the same impurity concentration as that of the vertical charge transfer channel layer
105
is shown in FIG.
15
B.
As indicated by a broken line in
FIG. 14A
, a deep depletion layer is formed in the vertical charge transfer channel layer under the electrodes (&PHgr;
3
and &PHgr;
4
) applied with a voltage HIGH, the depletion layer extending deep to the p-type semiconductor layer
108
. Another depletion layer indicated by the broken line is also formed in the vertical charge tr

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