Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-04-18
2003-01-21
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S066000, C216S078000, C438S720000, C438S742000
Reexamination Certificate
active
06509276
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to removal of metal material in integrated circuit devices, particularly removal of discrete portions of interconnect material.
2. Background
Integrated circuit structures are generally formed of hundreds or thousands of discrete devices on a semiconductor chip such as a silicon semiconductor chip. The individual devices are interconnected in appropriate patterns to one another and to external devices through the use of interconnection lines or interconnects to form an integrated device. Typically, many integrated circuit devices are formed on a single structure, such as a wafer substrate and, once formed, are singulated into individual chips or dies for use in various environments.
In the prior art, the predominant material for interconnect structures has been aluminum or an aluminum alloy. The material is generally introduced in the form of a deposition process, e.g., chemical vapor deposition (CVD), and patterned by way of an etching process. A typical aluminum interconnect patterning process, also referred to as an etching process, involves introducing a halogen species such as chlorine or bromine in the presence of oxygen and possibly a focused ion beam to interact with the interconnect material and selectively remove material. Patterning in this way allows typically lines of interconnect to be routed between devices in desired patterns.
In the context of forming improved integrated circuit chips or dies, researchers have recognized the benefit of copper or its alloys as an improved interconnect material. Copper and its alloys present unique challenges with respect to patterning. Copper, unlike aluminum, is not readily susceptible to a chemical etching processes. One solution to this patterning challenge has been met by Damascene processing in terms of introducing a copper interconnect according to a desired pattern. Once introduced, however, Damascene processing does not offer a technique for re-routing or modifying the introduction material.
In the context of forming integrated circuit dies or chips, the devices of such dies or chips are generally tested in a variety of ways prior to release or sale. In a typical process, an integrated circuit design is configured into a blueprint which is copied by complex machinery into a physical structure. Once defined, the physical structure is simulated prior to marketing. Due to pushing technology limits, simulation are generally not fully sufficient to represent actual product performance. Based on this reality, a physical structure of an original design product is fabricated (FAB) and the product enters a debug cycle.
During a product debug cycle, the integrated circuit product is tested against original design intent in an effort to correct any logical or speed test issues that are realized following FAB initial release. Debug laboratory tools are designed to reduce the debug cycle times as much as possible because a direct relationship exists between the debug cycle time and time-to-market.
One unique challenge to a debug laboratory seeking to evaluate and quite possibly modify or re-route copper-based interconnect routing, is that the existing tool set is not designed or configured to pattern (e.g., etch) copper material. What is needed is a process and tool that allows for such modification or re-routing of copper interconnect.
REFERENCES:
patent: 4243476 (1981-01-01), Ahn et al.
patent: 4490211 (1984-12-01), Chen et al.
patent: 4838994 (1989-06-01), Gulde et al.
patent: 5958799 (1999-09-01), Russell et al.
patent: 6322672 (2001-11-01), Shuman et al.
patent: 6407001 (2002-06-01), Scott
patent: 2001/0027917 (2001-10-01), Ferranti et al.
patent: 2001/0053605 (2001-12-01), Phaneuf et al.
J. Robert Lineback, “FEI Develops Circuit Editing Tool for Copper ICs”,Semiconductor Business News, Jun. 19, 2000.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Powell William A.
LandOfFree
Focused ion beam etching of copper with variable pixel spacing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Focused ion beam etching of copper with variable pixel spacing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Focused ion beam etching of copper with variable pixel spacing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3015943