Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-12-23
2003-04-01
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000
Reexamination Certificate
active
06542142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a voltage generating circuit, for example, a voltage generating circuit capable of outputting multi-level voltages having a plurality of different levels in accordance with input signals, a spatial light modulating element and a display system constituted by using the voltage generating circuit, and a driving method for display system having the spatial light modulating element.
2. Description of the Related Art
In a display system, for example, in a liquid crystal display, an image signal having predetermined luminance can be displayed by controlling the light intensity of each pixel in accordance with image information to be displayed. Therefore, it is necessary to provide, with respect to each pixel, an electrode for controlling a light modulating element constituting the pixel, and control the voltage of the corresponding electrode for changing the light modulation characteristic of each pixel in accordance with image information to be displayed. It is desired to provide a voltage generating circuit which generates a predetermined voltage in accordance with image information to be displayed by each electrode.
In a display which displays general image information such as image signals of television broadcast or image signals displayed on a computer monitor, a display screen is constituted by arraying an extremely large quantity of pixels. To control all the electrodes provided in accordance with these pixels, a voltage generating circuit which enables miniaturization, lower dissipation power and high-speed operation is required.
FIGS. 1A
to
1
E show exemplary structures of generally used voltage generating circuits.
FIG. 1A
is a circuit diagram of a load resistance type voltage generating circuit constituted by an nMOS transistor NT and a resistance element RL. As shown in
FIG. 1A
, an input signal Sin is supplied to the gate of the nMOS transistor NT, and the drain is connected to a power-supply voltage Vcc through the resistance element RL. The source is connected to a common electric potential Vss (or grounded).
Similarly,
FIG. 1B
is a circuit diagram of a load resistance type voltage generating circuit constituted by a pMOS transistor PT and a resistance element RL. As shown in
FIG. 1B
, an inversion signal/Sin of an input signal Sin is applied to the gate of the pMOS transistor PT, and the source of the pMOS transistor is connected to a power-supply voltage Vcc. The drain is grounded through a resistance element RL.
In the load resistance type voltage generating circuits shown in
FIGS. 1A and 1B
, a current flowing through the nMOS transistor NT or the pMOS transistor PT is set in accordance with the level of the input signal Sin or its inversion signal/Sin. Therefore, the level of an output signal Sout outputted from the drain of the nMOS transistor NT or the pMOS transistor PT is set by the input signal Sin or its inversion signal/Sin.
FIG. 1C
shows an example of a CMOS type voltage generating circuit constituted by a pMOS transistor PT
1
and an nMOS transistor NT
1
. As shown in
FIG. 1C
, both of the gates of the pMOS transistor PT
1
and the nMOS transistor NT
1
are connected to a terminal for an input signal Sin. The source of the pMOS transistor PT
1
is connected a power-supply voltage Vcc, and the source of the nMOS transistor NT
1
is connected to a common electric potential Vss. In addition, the drains of these two transistors are connected to each other, and the connection point becomes a terminal for an output signal Sout.
In the voltage generating circuit of
FIG. 1C
, the ON/OFF states of the pMOS transistor PT
1
and the nMOS transistor NT
1
are controlled in accordance with the input signal Sin, and the level of the output signal Sout is controlled accordingly. For example, when the input signal Sin is at a low level such as the level of the common electric potential Vss or a level proximate thereto, the pMOS transistor PT
1
is held in the ON state while the nMOS transistor NT
1
is held in the OFF state. Therefore, the output signal Sout is held at the level of the power-supply voltage Vcc. On the contrary, when the input signal Sin is at a high level such as the level of the power-supply voltage Vcc or a level proximate thereto, the pMOS transistor PT
1
is held in the OFF state while the nMOS transistor NT
1
is held in the ON state. Therefore, the output signal Sout is held at the level of the common electric potential Vss.
Thus, the voltage generating circuit of
FIG. 1C
supplies the output signal Sout having the inverted logical level of that of the input signal Sin.
FIG. 1D
is a circuit diagram of a buffer type voltage generating circuit constituted by a pMOS transistor PT
2
, an nMOS transistor NT
2
, and resistance elements RF
1
, RF
2
. As shown in
FIG. 1D
, both of the gates of the pMOS transistor PT
2
and the nMOS transistor NT
2
are connected to a terminal for an input signal Sin. The source of the pMOS transistor PT
2
is connected to a power-supply voltage Vcc, and the source of the nMOS transistor NT
2
is connected to a common electric potential Vss. In addition, the resistance elements RF
1
and RF
2
are connected in series between the drains of the pMOS transistor PT
2
and the nMOS transistor NT
2
, and the connection point of the resistance elements forms a terminal for an output signal Sout.
Similarly to the CMOS type voltage generating circuit of
FIG. 1C
, the voltage generating circuit of
FIG. 1D
provides the output signal Sout having an inverted logical level of that of the input signal Sin. In the voltage generating circuit of this example, the resistance elements RF
1
, RF
2
constitute feedback resistance elements, thus compensating temperature characteristics of the MOS transistors PT
2
, NT
2
. In general, a drain current of the MOS transistor has a negative temperature characteristic. By providing the resistance element for temperature compensation, the negative temperature characteristic of the drain current can be restrained.
FIG. 1E
is a circuit diagram of a DRAM type voltage generating circuit. As shown in
FIG. 1E
, the voltage generating circuit of this example is constituted by an nMOS transistor NT
2
with its source connected to a data line DL and with its gate connected to a control line CL, and a capacitor CS connected between the nMOS transistor NT
2
and a common electric potential Vss.
In accordance with a control signal inputted to the control line CL, the ON/OFF state of the transistor NT
2
is controlled. When the transistor NT
2
is in the ON state, a signal on the data line DL is outputted to the drain side of the transistor NT
2
, and the capacitor CS is charged accordingly. If a voltage drop of the transistor NT
2
can be ignored, the capacitor CS is charged to the same level as an input voltage of the data line DL. In addition, after the transistor NT
2
is set in the OFF state by the control signal of the control line CL, the level of an output signal Sout is held.
In order to enhance the driving capability in the case where a load circuit to be driven by the voltage generating circuit has a low impedance, the buffer of
FIG. 1D
can be provided on the output side of the voltage generating circuits of
FIGS. 1A
,
1
B and
1
E.
Meanwhile, the recent semiconductors have been becoming more advanced in features such as increase in operating speed, increase in integration, fine processing, and reduction in voltage. Among these features, the reduction in voltage provides an effect of square with respect to reduction in dissipation power (i.e., dissipation power ∝voltage
2
). Therefore, the reduction in voltage has been desired increasingly.
For example, since a liquid crystal display has a large number of long distributing electrodes, the electrode capacity is large. Moreover, since a signal of 10 V or more is usually handled, invalid dissipation power occupies a large part of charge/discharge of the stray capacitance. For example, if the driving voltage can be halved to 5 V, the charging/dischar
Akimoto Osamu
Yumoto Akira
Frommer William S.
Frommer & Lawrence & Haug LLP
Hjerpe Richard
Nguyen Kevin M.
Smid Dennis M.
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