Synchronous semiconductor memory device with NOEMI output...

Details Synchronous semiconductor memory device with NOEMI output... Synchronous semiconductor memory device with NOEMI output...

2002-09-25

2003-07-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050

Reexamination Certificate

active

06597630

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to synchronous semiconductor memory devices synchronized with a clock signal and particularly to configurations of output buffer circuits.
2. Description of the Background Art
In microfabrication of a transistor, scaling a device down is not always associated with accordingly scaling a power supply voltage down, and the power supply voltage can be maintained constant while the device's dimension can be reduced. In this case, the transistor provides an intense electric field in a vicinity of the drain. Hot carriers are thus produced in a channel and jump into a gate oxide film to impair the transistor's device characteristics disadvantageously. One approach to solve this problem is “Normally-On Enhancement MOSFET Insertion (NOEMI).”
FIG. 15
shows one example of an NOEMI output buffer circuit internal to an LSI.
With reference to
FIG. 15
, this NOEMI output buffer circuit operates in response to data signals TO, /OT to transmit data to an output terminal OP connected to an external bus. Data signals OT, /OT are complementary signals corresponding to data output from the LSI externally. Data signal/OT corresponds to an inverted version of data signal OT. Hereinafter similarly the mark “/” used with a signal will indicate an inverted version of the signal. For example, a signal /S is an inverted version of a signal S.
This output buffer circuit is provided with an n channel MOS transistor NT
2
connected between an output node NO of an inverter formed by a n channel MOS transistor NT
1
and a p channel MOS transistor PT
1
and a drain terminal of transistor NT
1
. Transistor NT
2
has its gate constantly receiving a power supply voltage VCC. Transistor NT
2
is thus constantly turned on. By the provision of transistor NT
2
the transistor NT
1
drain voltage is limited to a voltage Vd=Vg−Vth, wherein voltage Vg to a gate voltage of transistor NT
2
and voltage Vth corresponds to a threshold voltage Vth of transistor NT
2
.
The insertion of transistor NT
2
can thus limit a drain voltage applied to transistor NT
1
and thus prevent the transistor from having poor device characteristics attributed to injection of hot carriers.
FIG. 16
shows a configuration of a non-NOEMI output buffer circuit.
The
FIG. 16
circuit is identical in configuration to the
FIG. 15
circuit minus transistor NT
2
. It transmits to node NO the data corresponding to complimentary data signals OT, /OT.
FIG. 17
conceptually represents a region of a capacitance corresponding to a load (hereinafter also referred to as a “load capacitance”) of output node NO for the non-NOEMI output buffer circuit of FIG.
16
.
With reference to
FIG. 17
, transistors PT
1
and NT
1
are shown to form an output buffer circuit formed on a substrate. In a region shown in
FIG. 17
in which transistor PT
1
is formed the source's side is connected to power supply voltage VCC and the drain's side is connected to node NT
0
. The gate receives the level in voltage of data signal /OT input. In a region in which transistor NT
1
is formed the source's side is connected to a ground voltage GND and the drain's side is connected to node N
0
. The gate receives the level in voltage of data signal OT input. For this non-NOEMI output buffer circuit, output node NO is associated with a load capacitance corresponding to a region on the side of the drain of transistor PT
1
(a drain junction capacitance on the side of transistor PT
1
) and a region on the side of the drain of transistor NT
1
(a drain junction capacitance on the side of transistor NT
1
). More specifically, as shown in
FIG. 17
, a hatched region on the side of the drains of transistors PT
1
and NT
1
corresponds to a region of a load capacitance imposed on output node N
0
.
FIG. 18
conceptually represents a region of a load capacitance of output node N
0
for NOEMI output buffer circuit of
FIG. 15
with transistor NT
2
constantly turned on.
With reference to
FIG. 18
, transistors PT
1
, NT
1
and NT
2
are shown to form an NOEMI output buffer circuit formed on a substrate. As has been described previously,
FIG. 18
is different from
FIG. 17
in that transistor NT
2
is further provided on a substrate at a predetermined region in which an N-type transistor is formed.
Transistor NT
2
is provided between transistor NT
1
and node N
0
and the transistor NT
1
drain's side and the transistor NT
2
source's side are electrically coupled together. Transistor NT
2
has its gate receiving power supply voltage VCC and the transistor NT
2
drain's side is connected to node N
0
.
Node N
0
has a load capacitance imposed thereon, as follows: with its gate constantly receiving power supply voltage VCC, transistor NT
2
is constantly turned on and the capacitance of the gate of transistor NT
2
and that in a region closer to the drain of transistor NT
1
or the source of transistor NT
2
(an inter-gate junction capacitance) are added to node N
0
in addition to a drain junction capacitance of transistors PT
1
and NT
2
. Thus while the NOEMI output buffer circuit with transistor NT
2
constantly turned on can prevent injection of hot carriers it would disadvantageously introduce increased load capacitance.
This increased load capacitance is never negligible for memory systems having a high speed interface such as synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM and the like.
FIG. 19
shows a concept for implementing rapid data transfer in a memory system having a high speed interface. As shown in
FIG. 19
, LSIs each have output terminal OP electrically connected to an output node of an output buffer circuit and are connected in parallel to an external bus.
FIG. 20
compares data waveforms based on a difference between a load capacitance of output node N
0
of a non-NOEMI output buffer circuit and that of the node of an NOEMI output buffer circuit when data is transferred rapidly.
If the LSI is configured with the non-NOEMI output buffer circuit a small load capacitance is imposed on output terminal OP. Thus, as shown in
FIG. 20
, if data is transferred rapidly, with the small load capacitance imposed on output terminal OP, the data can be transmitted in a short period of time with a desired level. If the LSI has the NOEMI output buffer circuit then a load capacitance larger than for the non-NOEMI output buffer circuit is imposed on output terminal OP. As such, if data is rapidly transferred, with a large load capacitance imposed on output terminal OP, the data is hardly transmitted in a short period of time with a desired level. As a result, data transferred would provide a signal level lower than before the data is rapidly transferred. This can result in a detection portion internal to a system erroneously recognizing the transferred data.
SUMMARY OF THE INVENTION
The present invention contemplates a synchronous semiconductor memory device capable of rapid data transfer, having an NOEMI output buffer circuit with an output terminal free from significant load capacitance.
The present invention in one aspect provides a synchronous semiconductor memory device operating in synchronization with a clock signal, including a memory array, a control signal generation circuit, an output buffer circuit, and an output control circuit. The memory array has a plurality of memory cells arranged in rows and columns and each storing data. The control signal generation circuit receives an external instruction input in synchronization with the clock signal to generate a control signal for defining a data output period in response to the external instruction. The output buffer receives data read from the memory array for output to an output node during the data output period. Furthermore the output buffer circuit includes a first transistor connected between the output node and a first voltage, a second transistor connected between the output node and a second voltage, and a third transistor connected between the out

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