Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-02-09
2003-05-06
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S758000, C257S780000
Reexamination Certificate
active
06559540
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a flip-chip semiconductor device and a method of forming the same, and more particularly to a repairable flip-chip semiconductor device which allows that a non-defective flip-chip-mounted semiconductor device is once removed from a defective multilayer circuit board for repairing the non-defective flip-chip-mounted semiconductor device to a new non-defective multilayer circuit board for realizing a possible low manufacturing cost and a method of forming the same.
The conventional flip-chip semiconductor device comprises a semiconductor chip, wherein an array of external electrodes is provided either on a peripheral region of the semiconductor chip or an active region of the semiconductor chip, and further bumps are formed on the external electrodes. The bumps may, for example, comprise either solder bumps, Au bumps and Sn—Ag alloy bumps. The semiconductor device is flip-chip-bonded on a multilayer circuit board having electrode pads having the same patterns as the bumps of the semiconductor device. If the bumps comprise the solder bumps, then an infrared ray re-flow process using a flux is usually used for flip-chip-mounting the semiconductor device onto the multilayer circuit board. After the semiconductor device has been flip-chip-mounted onto the multilayer circuit board, then there is raised a serious problem with a temperature cyclic characteristic in the mounting reliability due to mismatch in linear expansion coefficient between the semiconductor device and the multilayer circuit board.
In order to improve the temperature cyclic characteristic, it had been proposed to make an expansion coefficient of the multilayer circuit board close to an expansion coefficient of the semiconductor device. Namely, it had been proposed to minimize the mismatch in linear expansion coefficient between the semiconductor device and the multilayer circuit board for improvement of the mounting reliability. For this purpose, ceramic based materials are used for the multilayer circuit board. Since, those ceramic based materials are, however, expensive, the applications of the conventional flip-chip semiconductor devices have been limited to super computers and large scale computers.
In recent years, inexpensive and large linear expansion coefficient organic materials have been used for the multilayer circuit board in place of the above expensive ceramic based materials, wherein an inter-space between the semiconductor device and the organic material multilayer circuit board is filled with an under-fill resin. The provision of the under-fill resin into the inter-space between the semiconductor device and the organic material multilayer circuit board results in relaxation or dispersion of a shearing stress applied to the bumps between the semiconductor device and the organic material multilayer circuit board, thereby improving the mounting reliability. The provision of the under-fill resin into the inter-space between the semiconductor device and the organic material multilayer circuit board allows the use of the inexpensive organic material multilayer circuit board. The use of the under-fill resin may raise the following problems. If any voids are present in the under-fill resin or if the under-fill resin has inferior adhesiveness with the interface of the semiconductor device or with the interface of the organic material multilayer circuit board. In a porosity re-flow process of the product, peeling may appear on the under-fill resin interfaces to the semiconductor device and to the organic material multilayer circuit board, whereby the yield is dropped. Indiscriminately, it can not be said that the provision of the under-fill resin into the inter-space between the semiconductor device and the organic material multilayer circuit board realizes the low manufacturing cost.
The flip-chip semiconductor chip is expensive. If the above temperature cyclic characteristics have been improved, then no problem may be raised. If, however, any defective appear on the other part than the semiconductor chip after the semiconductor chip has been mounted on the multilayer circuit board, then it is necessary to repair the non-defective semiconductor chip to a new non-defective multilayer circuit board instead of the defective multilayer circuit board. Once the under-fill resin is provided between the inter-space between the semiconductor chip and the multilayer circuit board, it is difficult to repair the non-defective semiconductor chip to a new non-defective multilayer circuit board. In this case, not only the defective semiconductor device but also the non-defective multilayer circuit board could not be used.
By contrast, if the ceramic-based material is used for the multilayer circuit board wherein the linear expansion coefficient of the ceramic-based material is optimized, then it is unnecessary to provide the under-fill resin into the inter-space between the semiconductor device and the multilayer circuit board. It is relatively easy to repair the non-defective semiconductor chip to a new non-defective multilayer circuit board.
FIGS. 1A through 1C
are schematic side views illustrative of sequential repair processes for removing the non-defective semiconductor chip from the defective multilayer circuit board. With reference to
FIG. 1A
, a non-defective semiconductor chip
101
with solder bumps
102
are flip-chip-mounted on a defective multilayer circuit board
110
. With reference to
FIG. 1B
, an adsorbing and heating tool
120
is made into contact with an opposite surface of the non-defective semiconductor chip
101
to the surface having the solder bumps
102
and facing to the defective multilayer circuit board
110
. The adsorbing and heating tool
120
has heaters
121
for heating the non-defective semiconductor chip
101
with the solder bumps
102
. The adsorbing and heating tool
120
is capable of vacuum adsorption with the non-defective semiconductor chip
101
and also the heaters
121
generate heats to be transmitted through the non-defective semiconductor chip
101
to the solder bumps
102
, whereby bonding portions of the solder bumps
102
to electrode pads of the defective multilayer circuit board
110
are melt. In this state, the adsorbing and heating tool
120
performing the vacuum adsorption with the non-defective semiconductor chip
101
is moved upwardly to remove the non-defective semiconductor chip
101
from the defective multilayer circuit board
110
. With reference to
FIG. 1C
, the non-defective semiconductor chip
101
is peeled from the defective multilayer circuit board
110
for subsequent repairing the non-defective semiconductor chip
101
to a new non-defective multilayer circuit board.
The non-defective semiconductor chip
101
is peeled from the defective multilayer circuit board
110
by the mechanical force due to the vacuum adsorption after the solder bumps
102
have sufficiently be heated by the heat conduction from the heaters
121
through the non-defective semiconductor chip
101
. The mechanical force may provide a certain mechanical damage to the solder bumps
102
on the non-defective semiconductor chip
101
and also provide a damage to barrier metal junction portions between the solder bumps
102
and the non-defective semiconductor chip
101
. Further, the mechanical force may provide a certain mechanical damage to a passivation film of a polyimide based organic material or silicon oxide which protects the active regions of the non-defective semiconductor chip
101
as well as provide a damage to the non-defective semiconductor chip
101
, whereby the non-defective semiconductor chip
101
becomes defective.
In Japanese laid-open patent publication No. 10-135270, it is disclosed to solve the above problem. After a passivation film is formed on a surface of a semiconductor region on which solder bumps are intended to be formed, an insulation film is further formed on the passivation film. External electrodes are formed on the insulating films over the passivation film. The solder bumps
NEC Electronics Corporation
Picardat Kevin M.
Young & Thompson
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