System and method for high-speed, synchronized data...

Pulse or digital communications – Synchronizers

Reexamination Certificate

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Details

C375S376000

Reexamination Certificate

active

06587525

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to data communication systems. More particularly, this invention relates to the recovery using oversampling in a receiving system of digital data transmitted via a high-speed link.
2. Description of Related Art
As electronic and computer technology continues to evolve, communication of information among different devices, either situated near by or at a distance becomes increasingly important. For example, it is now more desirable than ever to provide for high speed communications among different chips on a circuit board, different circuit boards in a system, and different systems with each other. It is also increasingly desirable to provide such communications at very high speeds, especially in view of the large amount of data required for data communications in intensive data consuming systems using graphical or video information, multiple input-output channels, local area networks, and the like.
It is particularly desirable to enable individual personal computers, workstations, or other computing devices, within which data is normally internally transferred using parallel data buses, to communicate with each other over relatively simple transmission lines. Such transmission lines typically include only one or two conductors, in contrast with the 64-bit and wider data paths within computing systems now commonly available.
A communication system that includes oversampling is often utilized to recover data transmitted data. Such a system includes a receiver which samples the incoming serial data stream at a rate greater than the rate at which symbols (bits) are being transmitted. For example, in a three-times (3×) oversampling receiver, the incoming data stream is sampled at a rate approximately three times the symbol rate. However, there are various problems to overcome in order to effectively implement such a receiver when the rate of data transmission is very high.
One problem is the difficulty in handling overflow and/or underflow of incoming data at the receiving end. For example, usually the output of a 3× oversampler contains sets of three consecutive 1s or 0s, but occasionally 4 or 2 consecutive 1s or 0s may occur. Such overflow and/or underflow will occasionally occur, for example, when the frequency of the local clock of the transmission system is not in precise synchronization with the local clock of the receiving system, when there is jitter in the sampling clock, and so on.
Other problems include difficulties in determining the correct symbol (bit) boundaries in the oversampled data stream and difficulties in determining the correct values of the symbols from the multiple samplings of each symbol.
SUMMARY OF THE INVENTION
The above described needs are met and problems are solved by the present invention. A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to-the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within 0.1% tolerance. In a normal flow situation, data frames are output by the receiver in alternate cycles of the system clock. In an overflow situation, data frames are output by the receiver in consecutive cycles of the system clock. In an underflow situation, data frames are not output by the receiver in consecutive cycles of the system clock.


REFERENCES:
patent: 4672639 (1987-06-01), Tanabe et al.
patent: 5430485 (1995-07-01), Lankford et al.
patent: 5587709 (1996-12-01), Jeong
patent: 5983287 (1999-11-01), Kuroiwa et al.
patent: 6229859 (2001-05-01), Jeong et al.
patent: 0 498 064 (1991-08-01), None
patent: WO 97/42731 (1997-11-01), None
Kyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog-Kyoon Jeong, Members, IEEE “A CMOS Serial Link For Fully Duplexed Data Communication”IEICE Transactions on Electronics E78-C (1995) No. 6, Tokyo, JP, 12 pages.

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