Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-05-09
2003-03-04
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S073100, C324S763010, C714S732000
Reexamination Certificate
active
06529030
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an IC testing apparatus in which a testing signal is inputted into a semiconductor device so that processing is carried out by the semiconductor device and the quality of the semiconductor device is judged by the result of processing. Also, the present invention relates to an IC testing method.
Conventionally, there is provided an IC testing apparatus for testing a semiconductor device having a correction circuit by which the wave-form of a signal inputted into the device to be tested is shaped and timing of the signal is corrected. Referring to
FIGS. 4
to
6
, the conventional IC testing apparatus having the correction circuit will be explained below.
FIG. 4
is an overall arrangement view showing an IC testing apparatus
100
which is an example of the conventional IC testing apparatus.
As shown in
FIG. 4
, the IC testing apparatus
100
includes: a pattern generator
2
for outputting a pattern signal
2
a
to test a device
3
to be tested; a circuit
20
for generating a testing signal
20
a
according to the pattern signal
2
a
outputted from the pattern generator
2
; an analog comparator
4
for comparing an output signal
3
a
, which has been obtained by the operation of the device
3
to be tested according to the testing signal
20
a
, with a reference voltage inputted from the outside; a digital comparator
5
for comparing a result of the comparison conducted by the analog comparator
4
with an expecting pattern which is an expecting result of the test; and a timing generator
6
for generating a timing signal to control the operation of the digital comparator
5
.
In this connection, in the device
3
to be tested of this IC testing apparatus
100
, the testing signal
20
a
is inputted into a predetermined pin, and the output signal
3
a
is outputted from the same pin. While the device
3
to be tested is being tested, a state in which the testing signal
20
a
is inputted into the device
3
to be tested and written in the device
3
is defined as “Write Mode”, and a state in which the output signal
3
a
is read out from the device
3
to be tested and outputted from the device
3
is defined as “Read Mode”.
The change-over between Write Mode and Read Mode is conducted by Write/Read change-over signal
2
b
outputted from the pattern generator
2
.
While Write/Read change-over signal
2
b
is showing Write Mode, the test pattern is outputted from the pattern generator
2
as the pattern signal
2
a
, and the circuit
20
creates the testing signal
20
a
according to this pattern signal
2
a
. This testing signal
20
a
is inputted into the device
3
to be tested, and the device
3
to be tested carries out a predetermined processing according to the testing signal
20
a.
After the device
3
to be tested has carried out the predetermined processing according to the testing signal
20
a
, Write/Read change-over signal
2
b
is changed over to Read Mode.
While Write/Read change-over signal
2
b
is showing Read Mode, an expecting pattern to expect the result of processing of the device
3
to be tested is outputted as the pattern signal
2
a
and inputted into the digital comparator
5
. The output signal
3
a
is outputted from the device
3
to be tested into the analog comparator
4
.
On the other hand, a reference voltage of “Hi” level is inputted into VOH input terminal
41
of the analog comparator
4
, and a reference voltage of “Lo” level is inputted into VOL input terminal
42
of the analog comparator
4
. The analog comparator
4
compares the signal level of the output signal
3
a
, which has been inputted from the device
3
to be tested, with the reference voltages of “Hi” and “Lo” levels.
The digital comparator
5
operates according to the timing signal generated by the timing generator
6
and compares the signal inputted from the analog comparator
4
with the expecting pattern inputted as the pattern signal
2
a
, so that the digital comparator
5
judges the quality of the device
3
to be tested.
Further, IC testing apparatus
100
includes TG/FC circuit
21
, which is arranged in the circuit
20
. TG/FC circuit
21
generates a timing signal by a predetermined period and shapes a wave-form of the pattern signal
2
a
according to this timing signal. A signal outputted from TG/FC circuit
21
is subjected to timing correction by the timing correcting circuit
23
.
The circuit
20
also includes TG/FC circuit
22
and the timing correcting circuit
24
. These TG/FC circuit
22
and timing correcting circuit
24
conduct shaping the wave-form of Write/Read change-over signal
2
b
and correcting the timing.
Signals subjected to timing correction by the timing correcting circuits
23
,
24
are inputted into the driver
25
.
Signals are inputted from the timing correcting circuits
23
,
24
into the driver
25
, and further reference voltages are inputted into VIH input terminal
26
and VIL input terminal
29
of the driver
25
. DENH signal
27
a
and DENL signal
28
a
are respectively inputted into DENH signal input terminal
27
and DENL signal input terminal
28
.
In this case, DENH signal
27
a
is a signal for setting so that the signal level of the testing signal
20
a
can be “Hi” level when the device
3
to be tested is in Read Mode.
DENL signal
28
a
is a signal for setting so that the signal level of the testing signal
20
a
can be “Lo” level when the device
3
to be tested is in Read Mode. In this connection when both DENH signal
27
a
and DENL signal
28
a
are at “Lo” level, the signal level of the testing signal
20
a
is in a state of high impedance.
FIGS. 5A
to
5
D are timing chart showing a state of each signal in the test of the device
3
to be tested. In
FIGS. 5A
to
5
D,
FIG. 5A
shows a pattern signal
2
a
,
FIG. 5B
shows a Write/Read change-over signal
2
b
,
FIG. 5C
shows DENH signal
27
a
and DENL signal
28
a
, and
FIG. 5D
shows a testing signal
20
a
. In this connection, “Hi” in the chart shows that the signal level of the testing signal
20
a
is at “Hi” level, “Lo” in the chart shows that the signal level of the testing signal
20
a
is at “Lo” level, and “HiZ” in the chart shows a state of high impedance.
When the test of the device
3
to be tested is started at time t
1
, the pattern generator
2
outputs a signal showing Write Mode as Write/Read change-over signal
2
b
and also outputs a test pattern as the pattern signal
2
a
. Accordingly, the test pattern is inputted into the device
3
to tested as the testing signal
20
a
. In this connection, although both DENH signal
27
a
and DENL signal
28
a
are at the level of “Lo” at this time, the testing signal
20
a
is not affected since Write/Read change-over signal
2
b
shows Write Mode.
When Write/Read change-over signal
2
b
is changed over to a signal showing Read Mode at time t
2
, an expecting pattern is outputted as the pattern signal
2
a
. In this connection, when both DENH signal
27
a
and DENL signal
28
a
are at the level of “Lo” at this time, the testing signal
20
a
is in a state of high impedance “Hiz”.
When Write/Read change-over signal
2
b
is changed over to a signal showing Write Mode at time t
3
, a test pattern is outputted as the pattern signal
2
a
until time t
4
. In this period from time t
3
to time t
4
, the state of each signal is the same as that in the period from time t
1
to time t
2
.
In the successive period from time t
4
to time t
5
, Write/Read change-over signal
2
b
shows Read Mode. Therefore, the expecting pattern is outputted as the pattern signal
2
a
. When one of DENH signal
27
a
and DENL signal
28
a
is at “Hi” level, the signal level of the testing signal
20
a
becomes a signal level corresponding to “Hi” level signal in DENH signal
27
a
and DENL signal
28
a.
FIG. 6
is a view showing a relation between the state of each signal and the operation of the driver
25
in IC testing apparatus
100
.
As shown in
FIG. 6
, the pattern of the testing signal
20
a
agrees with the pattern of the pattern signal
2
a
Ando Electric Co. Ltd.
Cuneo Kamand
Patel Paresh
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