Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2001-12-03
2003-03-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S622000, C438S618000
Reexamination Certificate
active
06528400
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a multilayer wiring structure formed by using a so-called damascene process and also to a technology that can effectively be applied to a semiconductor having such a multilayer wiring structure.
BACKGROUND OF THE INVENTION
In the current trend toward high performance micro-semiconductor devices, the multilayer wiring technology is indispensable for manufacturing such semiconductor devices. There is a well known technique of forming a wiring layer in a semiconductor integrated circuit by forming a thin film of a high melting point metal such as an aluminum (Al) alloy or tungsten (W) on an insulating film, subsequently forming on the thin film a resist pattern having a profile same as the wiring pattern to be produced there from the metal thin film by photolithography and then dry etching the thin film, using the resist pattern as mask. However, the technique of using an Al alloy or some other metal material has a major drawback that the wiring resistance rises remarkably to consequently increase the wiring delay and degrade the performance of the semiconductor device as the wiring is down-sized. Particularly, in the case of high performance logic LSIs, the drawback can severely damage the performance thereof.
As an attempt for bypassing this problem, there has been proposed a process of burying a wiring metal material containing copper (Cu) as principal conductor in the grooves formed on an insulating film and subsequently removing the unnecessary metal outside the grooves by means of a CMP (chemical mechanical polishing) technique to produce a wiring pattern in the grooves (so-called damascene process).
SUMMARY OF THE INVENTION
However, as a result of research efforts, the inventors of the present invention came to find that the damascene process, more particularly the dual-damascene process (for producing both the wiring and the interlayer connection wiring of a semiconductor device simultaneously after forming wiring grooves for wiring and contact holes for interlayer connections) is accompanied by a problem as described below that has not hitherto been known.
Firstly, either of two methods may be employed for forming groves (wiring grooves) and holes (connection holes) in the dual-damascene process; a hole-first method and a self-aligning method.
With the hole-first method, deep holes are firstly formed through an interlayer insulating film (which may be an inter-wire insulating film to be used for wiring) that is formed on a lower wiring layer until they get to the latter. To do this, a photoresist film patterned to show so may openings is formed on the interlayer insulating film and then the interlayer insulating film is dry etched by using the photoresist pattern as mask. Subsequently, the holes are filled with an anti-reflection material or resist and then wiring grooves are formed in the interlayer insulating film. To form wiring grooves, a photoresist film having opening for the grooves is formed on the interlayer insulating film and then the interlayer insulating film is dry etched using the photoresist pattern as mask. The holes are filled with the an anti-reflection material before forming the wiring grooves as described above in order to make the photoresist film for forming the wiring grooves to be accurately exposed to light and improve the processing accuracy. In other words, unless the holes are not filled with an anti-reflection material, the surface of the photoresist film reflects the profiles of the holes in the corresponding areas during the exposure operation to come to show undulations and no satisfactory surface flatness can be obtained. When the photoresist film is exposed to light with undulations on the surface, the light irradiating the photoresist pattern is scattered by the undulations (where the holes are formed) to make it no longer possible to accurately form the grooves in the interlayer insulating film. Particularly, because grooves may be formed in the holes (contact holes) for forming wires connecting the upper and lower wiring layers, the problem of poor processing accuracy occurs in many of those holes.
It is true that the problem that arises when the wiring groove pattern is exposed to light can be substantially dissolved by filling the holes with an anti-reflection material. Then the anti-reflection material left in the holes has to be removed after forming the wiring grooves. However, it is highly difficult to satisfactorily remove the filled material and the material remaining in the bottoms of the contact holes can give rise to a problem of insufficient connection or increased connection resistance between the upper and lower wiring layers. Particularly, the problem is ever more serious in recent year as a result of the trend of down-sizing semiconductor devices because the contact holes are also down-sized to give rise to an increased aspect ratio.
With the self-aligning method, on the other hand, wiring grooves and contact holes are formed in a manner as described below. An interlayer insulating film (which is not an inter-wire insulating film) is formed on the lower wiring layer and a silicon nitride film is formed thereon. Then, the silicon nitride film is subjected to a patterning process to produce holes and, thereafter, an inter-wire insulating film (which may typically be a silicon oxide film) is formed further thereon. In other words, an intermediary layer (silicon nitride film layer) processed to show a hole pattern is formed between the interlayer insulating film and the inter-wire insulating film. Then, a groove pattern is formed in the inter-wire insulating film. After the above process of forming the groove pattern, the inter-wire insulating film is subjected to a process of forming holes therethrough by using the intermediary layer (the silicon nitride film having a groove pattern) as mask. The self-aligning method is free from the problem of the residue of the material filled in the holes (contact holes) and that of poor processing accuracy that arises when the grooves are formed.
However, the intermediary layer is formed to operate as etching stopper in the process of forming the grooves (by etching) and also in the process of forming the holes and hence has to have a considerable film thickness. As a result of a study made by the inventors of the present invention, it was found that the intermediary layer is required to be at least about 100 nm thick if it operates properly. Silicon nitride is a highly dielectric material and operates negatively for reducing the dielectric constant of the interlayer insulating film and that of the inter-wire insulating film. A high dielectric constant between wires or between wiring layers gives rise to a large inter-wire capacitance, which by turn obstructs any attempt for realizing a high performance semiconductor device that operates at high speed. Additionally, since the holes are defined in the areas where both wires and holes are formed by dry etching, the holes produced there may have a reduced diameter when the mask for forming the holes and the one for forming the grooves are misaligned. Holes having a reduced diameter can obstruct the effort for providing the inter-wire connection wiring with a required level of resistance and hence again any attempt for realizing a high performance semiconductor device that operates at high speed.
If a large groove pattern is used to avoid the misalignment of the masks, it is no longer possible to reduce both the width of the wires and the distances separating the wiring layers to micro-dimensions. Therefore, the attempt for realizing a high performance semiconductor device will be baffled.
In view of the above identified circumstances, therefore an object of the present invention is to eliminate the residue of foreign objects that can be left in the contact holes of a semiconductor device in order to improve the reliability of the wire connections and the performan
Aoki Hideo
Fukada Shinichi
Hotta Shoji
Kobayashi Nobuyoshi
Nojiri Kazuo
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nhu David
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