Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-08-03
2003-09-02
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S122000, C348S294000
Reexamination Certificate
active
06614378
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique of realizing a sampling processing device suitable for digitization and IC-chip implementation.
2. Description of the Related Art
In general, digital signal processing devices perform various kinds of sampling processing. For example, a circuit shown in
FIG. 1
is an analog circuit that performs correlated double sampling that is used in image processing devices (e.g., ones for signal processing for a solid-state imaging device).
In processing circuit a shown in
FIG. 1
, an input signal Sin is branched into two parts at point A. One of the two parts is input to a first-stage sample-and-hold circuit b via a capacitor C
1
and then sent to (the positive input terminal of) an analog amplifier d via a second-stage sample-and-hold circuit c. The other part of the input signal Sin is input to a sample-and-hold circuit e via a capacitor C
2
and then sent to (the negative input terminal of) the analog amplifier d.
Receiving output signals of the respective sample-and-hold circuits c and e, the analog amplifier d outputs a result of an operation of taking the difference between the two output signals.
In
FIG. 1
, for the sake of convenience, “sample-and-hold circuit” is abbreviated as “S/H.” As for sample-and-hold pulse signals that are sent from a signal generation circuit (not shown) to the respective sample-and-hold circuits, a signal SH
1
is supplied to the sample-and-hold circuit b and a signal SH
2
is supplied to the sample-and-hold circuits c and e. For example, in signal processing for a solid-state imaging device, an imaging signal produced by the imaging device is supplied to this circuit as the input signal Sin. Reset voltages of the input signal Sin are sampled according to the signal SH
1
(a sample-and-hold signal for pre-charging portions) and signal voltages of the input signal Sin are sampled according to the signal SH
2
(a sample-and-hold signal for data portions).
An output signal of the above sampling processing circuit is subjected to quantization by an analog-to-digital conversion circuit.
However, because of the use of the analog amplifier d and the three sample-and-hold circuits b, c, and e and other factors, the above circuit has the following problems.
It is difficult to solve a problem of noise superimposition on a signal only by analog signal processing.
Because of difficulty in applying the CMOS manufacturing technology, it is difficult to implement the above circuit as a single IC (integrated circuit) chip in such a manner that it is combined with other circuits (e.g., an image signal processing circuit)
In view of the above, correlated double sampling processing circuits that perform digital processing have been proposed, which are disclosed in Japanese Patent Laid-open No. 266156/1999 and No. 13691/2000, for example.
However, the conventional circuits have various kinds of problems. For example, they require a high power supply voltage when digitized and they cannot provide a wide signal dynamic range. They also have a problem that they cannot be miniaturized because they require a field memory etc.
SUMMARY OF THE INVENTION
An object of the present invention is therefore to realize a sampling processing device that is simple in configuration and suitable for digitization and IC-chip implementation, and to solve problems that accompany the digitization.
To solve the above problems, the invention provides a sampling processing device comprising a sample-and-hold circuit, an analog-to-digital conversion circuit disposed downstream of the sample-and-hold circuit, a latch circuit disposed downstream of the analog-to-digital conversion circuit, and a calculation section for performing addition or subtraction on an input signal to the latch circuit and a delayed output signal of the latch circuit.
Therefore, the invention makes it possible to form a sampling processing device that has a simple configuration and is suitable for digital processing by using latch circuits without using a number of sample-and-hold circuits. The invention also makes it possible to implement a sampling processing circuit as one chip in such a manner that it is combined with other circuits.
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“Correlated Triple Sampling: A Digital Low-Noise Readout—Method for CCD'S”, Wey, H., Wang, Z., Guggenbuhl W., Melecon 1985/vol. II: Digital Signal Processing A. Luque, A.R. Figueiras Vidal, V. Cappellini (eds.) Elsevier Science Publishers B.V. (Notth-Holland) XP-002081182.
Kodake Toshiaki
Miyazaki Harutomi
Sato Yasushi
Jean-Pierre Peguy
Kanenen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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