Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2000-05-15
2003-09-30
Wu, Xiao (Department: 2774)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S087000
Reexamination Certificate
active
06628272
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention disclosed in this specification relates to the constitution of an apparatus suitable for generating signals for driving matrix type display devices of various types, display capacities and methods of display (for example, active matrix type liquid crystal display device).
2. Description of the Related Art
In recent years various matrix display devices are known. The most familiar one is a liquid crystal display device in which a simple (passive) display device and an active matrix display device are included. These devices can perform displaying operation by inputting an image signal and a clock (synchronizing) signal from outside. However, in respect of types of signals, there are various types in accordance with display devices and a normal signal needs to be modified and inputted in accordance therewith. This point differs significantly from a cathode ray tube (CRT) which is a typical conventional display device.
For example, an explanation will be given of an active matrix type display device as an example.
FIG. 10A and 10B
show a monolithic type active matrix display device having an active matrix portion
84
, a data driver circuit
82
and a scan driver circuit
83
on a substrate
81
where these circuits are formed at same plane of the substrate. However, even when the driver circuit is formed by a semiconductor chip, the explanation of the present invention remains unchanged.
The structure designated by
FIG. 10A
is of the simplest monochromatic display including a synchronizing signal input (CLOCK IN) and a video signal input (VIDEO IN) as input terminals. The structure is similar to that of a normal monochromatic CRT. (
FIG. 10A
)
Further, as shown by
FIG. 10B
, the structure of color display is provided with a synchronizing input (CLOCK IN) and video signal inputs (VIDEO IN B, G, R) in correspondence with three primary colors. The structure is similar to that of a normal color CRT. (
FIG. 10B
)
However, according to a matrix display device, input terminals other than these are provided and therefore, there are devices which need different drive signals.
For example, according to the structure shown by
FIG. 11A
, although the device is of a monochromatic display, a synchronizing signal input (CLOCK IN) and a first through a fourth video signal input (VIDEO IN
1
-
4
) are provided as input terminals. In a normal CRT, a number of inputs of video signals is only one in the monochromatic display, however, according to a matrix display device, there are cases where the video signal is divided into a plurality of signals in this way which are inputted simultaneously for the purpose of lowering processing speed of signals. (
FIG. 11A
)
Further, according to the structure shown by
FIG. 11B
, although the device is similarly of the monochromatic display, a first and a second synchronizing signal input (CLOCK IN
1
and
2
) and a video signal input (VIDEO IN) are provided as input terminals. According to a normal CRT, a number of inputs of synchronizing signals is only one, however, in a matrix display device, there are cases where a plurality of synchronizing signals phases of which are shifted from each other in this way are used and signal processing circuits (for example, shift registers
86
and
87
) respectively in correspondence thereto are provided for the purpose of lowering processing speed of signals. (
FIG. 11B
)
Similarly, according to the structure shown by
FIG. 11C
, a color display matrix having two routes of shift registers and dividing each of image signals in four, is provided with a first and a second synchronizing signal input (CLOCK IN
1
and
2
) and a first through a fourth video signal input (VIDEO IN R
1
-
4
, G
1
-
4
, B
1
-
4
) for each of three primary colors. (
FIG. 11C
)
For example, a data driver of a matrix display device having two routes of shift registers and performing display operation by video signals divided in eight, is provided with the structure shown by FIG.
12
. Further,
FIG. 13
shows pulse signals (for driving analog sample hold) outputted from shift registers A
1
and B
1
, a video signal before division and signals after division inputted to a first, a fourth and a ninth video signal line. (
FIG. 12
,
FIG. 13
)
As described above, according to the matrix display device, various display methods are requested in accordance with the constitution of circuit and the like. Further, there are such a variety of display methods (that is, drive signals) and accordingly, in performing inspection of various matrix display devices, it is necessary to remake circuits for generating drive signals for respective matrix display device. For example, a drive signal suitable for a display device shown by
FIG. 10A
can not drive the display devices shown by FIG.
11
A and
FIG. 11B
to carry out normal display.
However, to make a drive circuit for each of matrix display devices needs time and expense and hinders efficient operation. The present invention has been carried out in view of the above-described points and it is an object of the present invention to provide an apparatus capable of simply changing necessary drive signals in matrix display devices.
SUMMARY OF THE INVENTION
The present invention disclosed in this specification is featured in that signals for driving a matrix display device are generated by using the following three modules. That is,
a first module for inputting an image signal and a synchronizing signal (input module),
a second module for subjecting the image signal to time division
(image signal module), and
a third module for generating a clock signal (clock module).
These modules are independent from each other. The second module is featured in capable of arbitrarily setting a number of divisions of an image signal. For that purpose, a chip (sequencer chip) for controlling the setting operation may be exchanged or a programmable chip using a rewritable element of EPROM, EEPROM or the like may be used. Further, output and phase of the clock signal of the third module may by changed.
Various types of signals can be generated by combinations of the above-described modules. Further, a module having other function may be added. For example, there are a module (correction module, for example, &ggr; correction module) for correcting in compliance with initially set information, a module functioning as an interface (interface module) for connecting to a computer, a module for inputting and outputting a control signal from outside (control module), a module (trigger module) for connecting to an inspection circuit of an oscilloscope or the like, and so on.
When these modules can be used by inserting into a main frame
1
as shown by
FIG. 2
, wiring is facilitated.
FIG. 1
shows a state where various modules are inserted into the main frame
1
. That is, there are from left a control module
2
, an interface module
3
, &ggr; correction modules
4
-
6
, an input module
7
, an image module
8
, a clock module
9
, an image module
10
, a clock module
11
, an image module
12
, a clock module
13
and a trigger module
14
. (
FIG. 1
,
FIG. 2
)
The main frame is provided with for example, a power source common bus lines (particularly, clock distribution and timing synchronizing signals), which can be electrically connected to a back portion of the modules through connect pins. Also, each module is constituted with a sub-frame and at least one circuit board on which a circuit is provided.
Naturally, in using the main frame, the main frame needs not always to be filled with the modules but, for example, as shown by
FIG. 3
, may be in a state where a main frame
21
is inserted with from left an input module
22
, image modules
23
and
24
, a clock module
25
, image modules
26
and
27
, a clock module
28
, and image modules
29
and
30
and nothing is inserted thereto on the left side of the input module. (FIG.
3
)
REFERENCES:
patent: 5734378 (1998-03-01), Okada et al.
patent: 5923322 (1999-07-01), Kim
patent: 6084578 (2000-07-01)
Fish & Richardson P.C.
Wu Xiao
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