Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2001-06-01
2003-04-29
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C327S116000, C327S119000, C327S121000
Reexamination Certificate
active
06556644
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a frequency multiplier circuit and a method using above circuit for a period time division in subperiods of length as constant as possible, for a brushless motor.
DESCRIPTION OF THE RELATED ART
A brushless motor is a synchronous motor, the rotation of which is obtained by a current commutation in the windings in a way synchronous with the rotor position. It is necessary, therefore, to know exactly the rotor position to obtain the best accuracy in the motor working, and this position usually is deduced according two approaches: 1) by Hall effect position sensors; 2) by a counter-electromotive force signal (BEMF).
In this last driving choice the position information is completely stored in the BEMF's signal, i.e., in the case in which we have maximum BEMF we want to impose a maximum torque, in the case in which we have zero BEMF we want to impose a zero torque, and when we have a positive or negative BEMF we want to impose a positive or negative torque, respectively, and therefore, in order to drive multiphase brushless motors, we have to excite the motor's phases with voltage waveforms that are shifted 360
degrees out of phase with each other, where n is the number of phase. For example, in a three phase brushless motor, therefore, we have voltage waveforms that are shifted 360/3=120 degrees out of phase with each other and said waveforms are subdivided in a number of samples giving a step waveform able to approximate the driving waveform.
In
FIG. 1
a periodic time division in subperiods is shown.
As shown in such
FIG. 1
we note a first axis of abscissa describing a time dependent periodic signal T
c
and a second axis of abscissa describing a time division of said period T
c
in subperiods T
sys
. The T
c
signal points out a digital signal having period T
c
, suitably deduced from BEMF. The difference between period T
c
and the subperiods m*T
sys
generates what is commonly known as period reproduction error and in the particular case we have an error &egr; defined by the formula:
&egr;=
T
c
−m*T
sys
*INT[INT
(
T
c
/T
sys
)/
m]
with &egr; in a value range 0<&egr;<m T
sys
, where INT(num) is a function that rounds a number down to the nearest integer.
In a steady state, the signal period T
c
of the signal is time independent and the error &egr; committed in the reproduction of period T
c
and the reproduced period m*T
sys
, therefore formed by m subperiods, is a circuit evaluation parameter, that makes the measurement of the period T
c
.
Therefore the accuracy of the approximation of the motor driving waveform, a waveform that changes as a function of the connected loads, i.e., the possible range of values among which the error E can change, is a qualitative and quantitative parameter of the circuit and of the control method thereof.
SUMMARY OF THE INVENTION
In view of the state of the art described, it is an object of the present invention to estimate the period of a particular waveform by a fixed frequency timing signal and to reproduce said period by approximating subperiods as equally as possible to each other.
According to the present invention, such object is achieved by a frequency multiplier circuit comprising an input terminal arranged to receive a period signal, a timing frequency greater than the inverse of said period, a first counter circuit, implemented to execute counting at a fixed first frequency, proportional to said timing frequency, said first counter circuit coupled to a register, a second counter circuit implemented to execute counting at a second timing frequency, an adder configured to increase by one the content of said register of ADJ subperiods every 2
i
subperiods of said period, where ADJ is the value corresponding to the number i least significant bits of said register, so that the reproduction error of said period signal is as small as possible.
Furthermore, according to the present invention, such object is achieved by a frequency multiplier circuit comprising the following steps: a) accepting a timing frequency greater than of the inverse of said period length; b) executing counting by means of a first counter at a first fixed frequency proportional to said timing frequency; c) storing said counting in a register; d) executing counting by means of a second counter circuit at said timing frequency; e) increasing by one the stored value in said register during the ADJ subdivisions every 2
i
subdivisions of said period; f) comparing an output value of said register and an output value of said second counter; g) generating a second frequency such as to minimize the reproduction error.
Thanks to the present invention, it is possible to make a frequency multiplier circuit, and employ a method using the above circuit for period time division, for a brushless motor, able to reproduce the motor driving voltage waveform with an increased accuracy, making possible to improve the phase relationship between the applied profile and the motor position.
REFERENCES:
patent: 4851709 (1989-07-01), Bailey et al.
patent: 4959596 (1990-09-01), MacMinn et al.
patent: 6107843 (2000-08-01), de Gouy et al.
patent: 6157694 (2000-12-01), Larsson
Boutin, N. et al., “A Novel Frequency Multiplier,”IEEE Trans. on Instrumentation and Measurement, IM-35(4):566-570, Dec. 1986.
Bennett II Harold H.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Wambach Margaret R.
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