Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-11-06
2003-04-15
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
Reexamination Certificate
active
06548408
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of minimizing repetitive chemical-mechanical polishing scratch marks, to methods of processing a semiconductor wafer outer surface, to methods of minimizing undesired node-to-node shorts of a length less than or equal to 0.3 micron, and to semiconductor processing methods.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing is one technique utilized to process the outer surface of various layers formed over a semiconductor wafer. One principal use of chemical-mechanical polishing is to render an outer wafer surface of a layer or layers to be more planar than existed prior to starting the polishing. Only some or all of the outermost layer being polished might be removed during such a process.
In chemical-mechanical polishing, both the wafer and the pad which polishes the wafer are typically caused to rotate, typically in opposite directions, during the polishing action. A liquid slurry is received intermediate the wafer and the polishing pad. The slurry comprises a liquid solution, typically basic, and a solid grit material, typically constituting particles of a consistent size (i.e., within 5 nanometers of a size selected from around 25 to 100 nanometers in diameter). The action of the liquid solution and grit within the slurry intermediate the wafer and pad imparts removal of outer wafer layers utilizing both chemical and mechanical actions.
Semiconductor wafer processing continues to strive for ever increasing miniaturization and circuit density. Consequently, the separation distance between circuit components needing to be electrically isolated continues to shrink. For example, fabrication of integrated circuitry typically involves forming electrically isolated active areas from the semiconductive material of the wafer. The isolation is achieved by forming insulating isolation regions between discrete active areas. The isolation regions are typically formed from an oxide material which is either grown or deposited over the wafer. In the recent past, a technique referred to as shallow trench isolation has emerged as one way of providing isolation regions for the ever decreasing geometries. Here, a series of shallow trenches (i.e., one micron or less in depth) are formed within a substrate by patterning and etching. The trenches are subsequently filled with an oxide material, most typically deposited by a high density plasma deposition. The oxide is subsequently planarized by chemical-mechanical polishing, for example as described above. This forms discrete active area regions separated by isolation oxide.
As the separation between active areas fell to and below 0.3 micron, ever increasing and unacceptable circuit failures were discovered. This of course reduces yield and accordingly requires discarding of an increasing volume of potentially salable product.
SUMMARY OF THE INVENTION
In but one aspect of the invention, a method of minimizing repetitive chemical-mechanical polishing scratch marks from occurring on a polished semiconductor wafer surface resulting from breaking away of surface peaks having an elevation of at least 400 nanometers above an outer surface immediately adjacent said peaks comprises improving adherence of said peaks to the wafer by filling at least a portion of the volume between adjacent peaks with a material and chemical-mechanical polishing the peaks and the material at the same time.
In another aspect, a method of minimizing undesired node-to-node shorts of a length less than or equal to 0.3 micron formed laterally along an insulating dielectric layer in a monolithic integrated circuit chip comprises depositing a sacrificial layer of material over the dielectric layer and chemical-mechanical polishing completely through the sacrificial layer and into the dielectric layer prior to depositing any metal over the insulating dielectric layer.
In but another aspect, a semiconductor processing method comprises observing repetitive scratch marks on a chemical-mechanical polished surface of a first material on a first semiconductor wafer in process. On a plurality of semiconductor wafers processed subsequently to the first, a second material is formed over the first material and chemical-mechanical polishing the first and the second materials at the same time and reducing occurrence of said scratch marks at least partially thereby, the second material being different from the first.
These and other aspects are described below.
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Anderson Matthew
Micro)n Technology, Inc.
Utech Benjamin L.
Wells St. John P.S.
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