Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-04-22
2003-09-23
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000, C341S144000
Reexamination Certificate
active
06624779
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to an improved switched capacitor integrator circuit.
BACKGROUND OF THE INVENTION
For low power, it is desirable to share the input and reference capacitors in a switched-capacitor integrator. Unfortunately, this means that the circuit driving the integrator input must discharge this capacitor of the reference charge left over from the previous cycle, then charge it with the input signal. This requires higher bandwidth and power from the driver.
For low power, it is desirable to share a single switched capacitor at the input of an integrator for both the signal input and the reference capacitor. This reduces the total input capacitance by a factor of 4 (for the same KT/C noise) and greatly reduces the load, which the integrator's opamp must drive, thereby allowing it to use less power. Unfortunately, this capacitor sharing causes a few problems. One is the fact that the circuit which drives the input to the integrator must not only charge the input capacitor with signal charge, it must also discharge this capacitor of the charge left on the capacitor from the reference feedback of the previous half-cycle. Normally this would require a high-bandwidth (high power) driving circuit to charge this capacitor.
SUMMARY OF THE INVENTION
A switched capacitor integrator that shares a switched capacitor at the input of the integrator for the signal input and the reference capacitor. The operation of the circuit includes discharging the capacitor with a first clock signal; transferring an input voltage onto the capacitor with a second clock signal; applying a reference voltage to a first end of the capacitor with a third clock signal; and coupling a second end of the capacitor to the integrator with the third clock signal while the reference voltage is applied to the first end of the capacitor.
REFERENCES:
patent: 5574457 (1996-11-01), Garrity et al.
patent: 5894284 (1999-04-01), Garrity et al.
patent: 5990819 (1999-11-01), Fujimori
patent: 6087970 (2000-07-01), Panicacci
patent: 6148048 (2000-11-01), Kerth et al.
patent: 6304608 (2001-10-01), Chen et al.
patent: 6362770 (2002-03-01), Miller et al.
Brady III W. James
Mai Lam
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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