Semiconductor memory device having plate lines and precharge...

Details Semiconductor memory device having plate lines and precharge... Semiconductor memory device having plate lines and precharge...

2002-02-20

2003-04-22

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Low workfunction layer for electron emission

C365S149000, C365S184000, C365S203000, C365S205000, C365S226000, C257S337000

Reexamination Certificate

active

06552357

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having plate lines and precharge circuits.
As illustrated in
FIG. 1
, a semiconductor memory such as a DRAM (dynamic RAM) includes one MOS transistor Q for data transfer and one capacitor C for data storage. The drain of the MOS transistor is connected to a bit line BL, the source thereof is connected to one electrode of the capacitor, and the gate thereof is connected to a word line WL. A connecting point of the source of the MOS transistor Q and the one electrode of the capacitor C serves as a storage node N. The other electrode opposed to the one electrode with a capacitor insulation film interposed therebetween, serves as a plate electrode PL common to a plurality of capacitors C. A potential of, e.g., Vcc/2 is applied from a plate potential generator
10
to the plate electrode PL. The above DRAM is described in Kirihata et al., “Flexible Test Mode Approach for 256-Mb DRAM”, IEEE Journal of SOLID-STATE Circuits, Vol. 32, No. 10, October, 1997, pp. 1525-1534.
In a selected memory cell of the foregoing DRAM, the MOS transistor Q is turned on to charge/discharge the capacitor C in the sense/write mode. The potential variations of the storage node N vary the potential of the plate electrode PL and, in other words, noise remains on the plate electrode PL. More specifically, when data “0” is written to a memory cell in which data “1” (=Vcc) has been stored, the plate potential is varied as shown in FIG.
2
. In the case of
FIG. 2
, the potential amplitude of the bit line BL is changed between Vcc (e.g., 3.3V) and Vss (e.g., 0V), the precharge potential and plate potential of the bit line BL are each set at Vcc/2, and the word line WL is driven at boost potential Vpp (e.g., 4.5V). When the potential of the word line WL rises and the MOS transistor Q turns on, the capacitor C is set in a discharge mode, and the storage node N is decreased in potential, while the bit line BL is charged by the capacitor C and thus increased in potential. In this case, the potential of the plate electrode PL is slightly lowered by capacitance coupling between the plate electrode PL and the electrode alongside the storage node N of the capacitor C. When a sense amplifier starts to operate, the potential variations of the bit line BL are amplified and thus the potentials of both the bit line BL and storage node N are increased to Vcc. As the potential of the storage node N increases, the plate potential slightly increases. When a write operation starts, write data “0” is transferred to the bit line BL, and the potentials of the bit line BL and storage node N are each dropped to a Vss level. In response to the variations in potential, the plate potential slightly lowers and then gradually returns to a Vcc/2 level.
As described above, the plate potential varies with an access operation of the memory cells. The variation &Dgr;VPL of the plate potential is expressed by the following equation (1) using the potential variation. &Dgr;VSN of the storage node N:
&Dgr;
VPL=&Dgr;VSN×
(
Cs/CPL
)  (1)
where Cs is capacitance of the capacitor C and CPL is capacitance of the plate electrode PL (the sum of capacitance of capacitors C sharing one plate electrode PL).
Since the capacitance Cs of the capacitor C is smaller than that CPL of the plate electrode PL, an influence of potential variations of one storage node N upon the plate potential is small. If, however, the potentials of plural storage nodes N are varied in the same direction at the same time, the variation &Dgr;VPL of the plate potential cannot be ignored. In
FIG. 2
, the plate potential is almost recovered by one cycle of a selected word line (row cycle: a period during which the word line rises from Vss to Vpp, decreases to Vss and then start to rise next); however, there is a case where the plate potential cannot be recovered within the row cycle because of the resistance of the plate electrode itself, the resistance of wiring between the plate potential generator
10
and plate electrode PL, and the current driving performance of the generator
10
. In particular, as the DRAM increases in degree of integration, the electrodes of capacitors C sharing one plate electrode PL increases in number and the capacitance of the plate electrode PL becomes large. Furthermore, the wiring is thinned and lengthened and its resistance between-the plate potential generator
10
and the plate electrode PL is heightened. In the row cycle, therefore, the plate potential is more and more difficult to recover.
If a memory cell includes a capacitor C having a large leak, the storage node N and plate-electrode PL are short-circuited. Usually such a memory cell is treated as a defective and replaced with a spare memory cell by a redundancy circuit. This defective memory cell is not used for data storage. Since, however, the defective memory cell is not separated from the bit line, the potential variations of the bit line are directly applied to the plate electrode in the sense/write mode, thereby causing great variations in plate potential.
An influence of the above plate potential variations will now be described in detail. Under the circumstance where the plate potential is not varied, the readout voltage Vsense of the bit line BL is expressed by the following equation (2):
V
sense=(
V
cell−
VBL
)×{
Cs/
(
Cb+Cs
)}  (2)
where Vcell is potential of the storage node N immediately before the potential of the word line WL rises, VBL is precharge potential of the bit line BL, Cs is capacitance of the capacitor C, and Cb is capacitance of the bit line BL.
If the plate potential varies only by &Dgr;VPL, then the readout voltage Vsense of the bit line BL is given by the following equation (3):
V
sense=(
V
cell+&Dgr;
VPL−VBL
)×{
Cs/
(
Cb+Cs
)}  (3)
If the plate potential varies to lower (&Dgr;VPL<0), the readout potential of data “0” (Vcell=Vss) decreases and the readout voltage (potential difference) increases in the sense mode. Since, however, the readout potential of data “1” also decreases, a margin for reading data “1” is reduced. If, by contraries, the plate potential varies to rise (&Dgr;VPL>0), a margin for reading data “0” is reduced in the sense mode.
If the word lines are selected in sequence for high-speed row access, the sense amplifier is operated frequently; therefore, an amount of noise superimposed upon the plate electrode PL is increased and a malfunction will easily be caused due to a reduction in margin. This is one factor which prevents the DRAM from operating at high speed.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device capable of suppressing potential variations of a plate electrode.
Another object thereof is to provide a semiconductor memory device capable of high-speed access without reducing a margin for readout operations even by potential variations of a plate electrode.
To attain the above objects, according to a first aspect of the present invention, there is provided a semiconductor memory device comprising bit lines, word lines crossing the bit lines, memory cells arranged at intersections of the bit lines and word lines, and including a plurality of capacitors to which a plate electrode is connected in common, an insulation film formed on the plate electrode, a bit-line precharge circuit for precharging the bit lines, and a wiring layer formed on the insulation film and electrically connected to the plate electrode and a power supply terminal of the bit-line precharge circuit.
In the semiconductor memory device so constituted, if the plate electrode common to the capacitors of memory cells is used as power supplies of the bit-line precharge circuits, the potential variations of the plate electrode are suppressed. When the plate potential varies, the precharge potential of the bit lines varies accordingly and these variations are canceled each other at a readout

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