Metal working – Method of mechanical manufacture – Electrical device making
Patent
1995-06-05
1998-10-13
Echols, P. W.
Metal working
Method of mechanical manufacture
Electrical device making
29842, 29845, H05K 330, H01R 900
Patent
active
058194037
ABSTRACT:
A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads. A method of manufacturing a semiconductor die carrier includes the steps of individually manufacturing a plurality of electrically conductive leads without use of a lead frame; extending a plurality of the electrically conductive leads from at least one of a plurality of electrically insulative side walls; positioning a semiconductor die such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and electrically connecting the semiconductor die to corresponding ones of the electrically conductive leads.
REFERENCES:
patent: 3337838 (1967-08-01), Damiano et al.
patent: 3366915 (1968-01-01), Miller
patent: 3444506 (1969-05-01), Wedekind
patent: 3545606 (1970-12-01), Bennett
patent: 3676748 (1972-07-01), Kobayashi et al.
patent: 4487463 (1984-12-01), Tillotson
patent: 4572604 (1986-02-01), Ammon et al.
patent: 4616406 (1986-10-01), Brown
patent: 4655526 (1987-04-01), Shaffer
patent: 4675472 (1987-06-01), Krumme et al.
patent: 4698663 (1987-10-01), Sugimoto et al.
patent: 4734042 (1988-03-01), Martens et al.
patent: 4766479 (1988-08-01), Krum et al.
patent: 4897055 (1990-01-01), Jurista et al.
patent: 4931908 (1990-06-01), Boucard et al.
patent: 4943846 (1990-07-01), Shirling
patent: 4975066 (1990-12-01), Sucheski et al.
patent: 4989318 (1991-02-01), Utunomiya et al.
patent: 4991291 (1991-02-01), Koepke et al.
patent: 4997376 (1991-03-01), Buck et al.
patent: 5008734 (1991-04-01), Dutta et al.
patent: 5022144 (1991-06-01), Hingorany
patent: 5037311 (1991-08-01), Frankeny et al.
patent: 5049974 (1991-09-01), Nelson et al.
patent: 5071363 (1991-12-01), Reylek et al.
patent: 5081563 (1992-01-01), Feng et al.
patent: 5091772 (1992-02-01), Kohara et al.
patent: 5123164 (1992-06-01), Shaheen et al.
patent: 5137456 (1992-08-01), Desai et al.
patent: 5138438 (1992-08-01), Masayuki et al.
patent: 5182853 (1993-02-01), Kobayashi et al.
patent: 5259111 (1993-11-01), Watanabe
patent: 5281151 (1994-01-01), Arima et al.
patent: 5285104 (1994-02-01), Kondo et al.
patent: 5309024 (1994-05-01), Hirano
patent: 5326936 (1994-07-01), Taniuchi et al.
patent: 5331514 (1994-07-01), Kuroda
patent: 5334279 (1994-08-01), Gregoire
patent: 5342999 (1994-08-01), Frei et al.
patent: 5344343 (1994-09-01), Seidler
patent: 5351393 (1994-10-01), Gregoire
patent: 5371404 (1994-12-01), Juskey et al.
patent: 5376825 (1994-12-01), Tukamoto et al.
patent: 5390412 (1995-02-01), Gregoire
patent: 5422514 (1995-06-01), Griswold et al.
patent: 5543586 (1996-08-01), Crane, Jr. et al.
patent: 5659953 (1997-08-01), Crane, Jr. et al.
patent: 5696027 (1997-12-01), Crane, Jr. et al.
George D. Gregoire, "3-Dimensional Circuitry Solves Fine Pitch SMT Device Assembly Problem;" Connection Technology.
Dimensional Circuist Corporation, Dimensional Circuits Corp. Awarded Two U.S. Patents, D.C.C. News, Apr. 5, 1994.
George D. Gregoire, "Very Fine Line Recessed Circuitry -A New PCB Fabrication Process".
Robert Barnhouse, "Bifurcated Through-Hole Technology -An Innovative Solution to Circuit Density," Connection Technology, pp. 33-35 (Feb. 1992).
"AMP-ASC Interconnection Systems," AMP Product Information Bulletin, pp. 1-4 (1991).
"Micro-Strip Interconnection System," AMP Product Guide, pp. 3413-3414 (Jun., 1991).
"Rib-Cage II Through-Mount Shrouded Headers" and Micropax Board-to-Board Interconnect System.
Du Pont Connector Systems Product Catalog A, pp. 2-6, 3-0, 3-1 (Feb. 1992).
R.R. Tummala et al., "Microelectronics Packaging Handbook," Van Nostrand Reinhold, 1989, pp. 38-43, 398-403, 779-791, 853-859, and 900-905.
"Packaging," Intel Corporation, 1993, pp. 2-36, 2-96, 2-97, 2-100, 3-2, 3-24, and 3-25.
J.W. Blade et al., "New Chip Carrier Package Concepts," Computer, Productivity and Automation, IEEE Computer Society, vol. 10, pp. 58-68, (Dec., 1977).
Technical Disclosure Bulletin, vol. 32, No. 10A, Mar. 1990.
Crane, Jr. Stanford W.
Portuondo Maria M.
Echols P. W.
The Panda Project
LandOfFree
Method of manufacturing a semiconductor chip carrier does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor chip carrier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor chip carrier will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-300414