Pulse or digital communications – Testing – Signal noise
Reexamination Certificate
1998-12-18
2003-04-15
Pham, Chi (Department: 2631)
Pulse or digital communications
Testing
Signal noise
Reexamination Certificate
active
06549573
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of testing an A/D converter, a storage medium storing a program to test an A/D converter, and an apparatus for testing an A/D converter for glitch noise.
2. Related Background Art
A differential non-linearity (hereinafter, abbreviated to DNL) is used as a representative value showing converting characteristics of an A/D converter. At present, there is a histogram method as a general DNL testing method. According to the histogram method, as shown in
FIG. 6B
, a signal having a ramp waveform
2
of
FIG. 6A
is inputted to an input terminal of an A/D converter
1
and an A/D conversion is performed at a clock frequency which is fairly higher than that of the input ramp waveform. Each code of converted digital output data
3
is as shown in FIG.
6
C. The number of times of generation of each code converted by a clock corresponds to the DNL between the conversion bits. Therefore, as shown in
FIG. 6D
, a histogram in which an axis of abscissa shows a digital output code and an axis of ordinate indicates the number of conversions is obtained. As shown in
FIG. 6D
, a mean value
4
of the numbers of conversions of all of the digital output codes corresponds to 1 LSB of the A/D converter
1
. The value having the largest difference among the numbers of conversions of the codes for the mean value
4
is set to the DNL of the A/D converter. The histogram method has an advantage such that even if random noises are mixed into an input signal or the like upon testing, by getting the mean value of the histograms due to the repetition of a few times, the noises can be reduced and a DNL test can be performed at relatively high precision.
However, such a histogram method has the following problem. As shown in
FIG. 7A
, in an A/D converter for generating a glitch noise
5
in output data, the glitch noise of the n-th bit is hidden in the digital output code of the (n+2)-th bit, as shown in FIG.
7
B. Therefore, it is difficult to find a defect.
There is also a drawback such that in the case where the standard of the DNL of the A/D converter is equal to or less than −1 LSB, a defect in which monotonousness (data changes one bit by one in a manner such that the (n+1)-th bit appears after the n-th bit) is missing occurs, for example, in the case where the (n+2)-th bit comes after the n-th bit, the histogram data of the (n+1)-th bit is equal to 0, the DNL of the (n+1)-th bit is equal to (0-1 LSB)=−1 LSB, and the monotonousness of the A/D converter cannot be guaranteed.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to solve the foregoing problems and to provide a method of testing an A/D converter, a storage medium storing a program to test an A/D converter, and an apparatus for testing an A/D converter for glitch noise.
To accomplish the above object, according to the invention, a signal of a ramp waveform is inputted to an A/D converter, a difference between a digital output code outputted from the A/D converter and another digital output code obtained by shifting the output code by predetermined clocks is obtained, and a glitch is detected on the basis of a peak value of such a difference.
Preferably, the predetermined clocks are one clock.
Preferably, when the peak value of the difference exceeds a range of ±1, it is determined that the glitch has occurred.
Preferably, when an amplitude of the peak value of the difference exceeding the range of ±1 on the plus (+) side does not coincide with that on the minus (−) side, it is decided that a glitch noise has occurred at a change point of the relevant bit of the output code. When those amplitudes coincide, it is determined that the glitch noise has occurred in a flat portion of the relevant bit of the output code.
Preferably, a testing apparatus of a glitch noise of the invention comprises: means for inputting a signal having a ramp waveform to an A/D converter; two memory means for storing digital output data from the A/D converter; means for calculating a difference between the output data read out from one of the memory means in response to a clock and the output data read out from the other memory means in response to a clock obtained by shifting by predetermined clocks; and means for detecting a glitch on the basis of a peak value of the difference obtained by the calculation.
Preferably, a testing apparatus of a glitch noise of the invention comprises: means for inputting a signal having a ramp waveform to an A/D converter; two arrays each for storing digital output data from the A/D converter by shifting by predetermined clocks; means for calculating a difference between the output data which was read out from the two arrays and shifted by the predetermined clocks; and means for detecting a glitch on the basis of a peak value of the difference obtained by the calculation.
Preferably, there is provided a storage medium in which a detecting program for detecting a glitch noise of an A/D converter to which a signal having a ramp waveform was inputted has been stored, wherein the detecting program allows a computer to: store digital output data from the A/D converter into two arrays so as to be shifted by predetermined clocks; calculate a difference between the output data which was read out from the two arrays and was shifted by the predetermined clocks; and detect a glitch on the basis of a peak value of the difference obtained by the calculation.
According to the invention, the glitch noise which cannot be detected by only the histogram method can be detected at high precision. Further, an amplitude of the glitch noise, a generating position, and a generating position (whether it is a change position of bits or a flat portion) on the relevant bit can be known.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.
REFERENCES:
patent: 5581568 (1996-12-01), Togami
Burd Kevin M
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Pham Chi
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