Integrated socket for microprocessor package and cache memory

Details Integrated socket for microprocessor package and cache memory Integrated socket for microprocessor package and cache memory

2002-02-21

2003-09-30

Ta, Tho D. (Department: 2833)

Electrical connectors

Preformed panel circuit arrangement, e.g., pcb, icm, dip,...

With provision to conduct electricity from panel circuit to...

C439S061000, C439S065000, C439S540100, C439S485000, C439S946000, C361S752000

Reexamination Certificate

active

06626681

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to sockets used to connect microelectronic device packages to circuit boards. More particularly, the present invention relates to a socket which accommodates both a microprocessor package and cache memory.
BACKGROUND OF THE INVENTION
Modern computer systems include at least one microprocessor or other similar controlling device, and memory, commonly including several levels of cache memory. One type of cache memory is located on the same die as the microprocessor and is referred to as Level
1
or “L
1
” cache. Typically, the L
1
cache includes a very small amount of memory but can be accessed very quickly by the microprocessor due to its proximity to the microprocessor. Another type of cache, known as Level
2
or “L
2
” cache, is normally mounted in the same package as the microprocessor but on a different die. L
2
cache typically includes more memory than the L
1
cache but cannot be accessed as quickly. A third level of cache, known as Level
3
or “L
3
” cache, is normally mounted on a separate circuit board or circuit card from the microprocessor package and typically includes more memory than the L
1
and L
2
caches. However, the L
3
cache cannot be accessed as quickly as the L
1
and L
2
caches, due to its greater distance from the microprocessor.
FIG. 1
shows an example of an L
3
cache card design. An L
3
cache die can be assembled in a wire-bond or flip-chip type of package, and the package can be surface-mounted on a printed circuit board (PCB) card. Alternatively, the L
3
-cache die can be directly mounted on a PCB card with or without encapsulate. Hence, the illustrated design includes a PCB card
1
, on which one or more cache memory dies (or packages containing such dies)
2
are mounted, and edge fingers
3
to allow the PCB card to be inserted into an edge connector on a motherboard.
FIG. 2
shows how the L
3
cache card of
FIG. 1
can be installed in a computer system. The L
3
cache card
1
can be inserted into an edge connector
21
that is mounted on the motherboard
22
, a shown. Also mounted on the motherboard
22
is a socket
23
, which allows the microprocessor package
24
to be coupled to the motherboard
22
. A heat sink
25
is thermally coupled to the microprocessor package through a package heat spreader
26
.
The design of
FIGS. 1 and 2
has several disadvantages. First, the distance between the microprocessor package and the L
3
cache is undesirably large, which increases the L
3
cache access time. The L
3
cache card also consumes additional space and requires edge connectors on the motherboard. Further, the L
3
cache card tends to block some of the airflow through the heat sink, hindering the cooling of other components, such as microprocessor, chipset, and voltage regulators.
An alternative approach is to mount the L
3
cache on the same microprocessor package, like a multi-chip module (MCM). However, the cost of such an approach is very high and manufacturing is difficult.


REFERENCES:
patent: 2701346 (1955-02-01), Powell
patent: 3591834 (1971-07-01), Kolias
patent: 5303121 (1994-04-01), Thornberg
patent: 5859538 (1999-01-01), Self
patent: 6147871 (2000-11-01), DeWitt et al.
patent: 6203365 (2001-03-01), Wu
patent: 6261104 (2001-07-01), Leman
patent: 6328605 (2001-12-01), Walker et al.
patent: 6347039 (2002-02-01), Lee
patent: 1229209 (1989-12-01), None

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