Extended length counter chains in FPGA logic

Details Extended length counter chains in FPGA logic Extended length counter chains in FPGA logic

2001-10-08

2002-10-22

Wambach, Margaret R (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Compensation for excess or shortage of pulses

C377S116000

Reexamination Certificate

active

06470064

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to gate array logic. More specifically, the present invention relates to counter chains that may be implemented in field programmable gate array logic.
2. Description of the Related Art
The maximum length of prior art counter chains was limited by the carry-forward ripple delay through the chain. Typical field programmable logic arrays (FPGAs) include variable length counter chains with a serial carry look-ahead output. These variable length counter chains are linked together with the carry look-ahead output of one counter chain stage being passed to a carry input of the next counter chain stage. When the individual stage delay, as multiplied by the number of stages in a counter, exceeded the period between clocks, the counter would no longer count correctly. Further, even if these counters include fast look-ahead logic, there remains the fundamental counter chain length limitation that the overall carry delay, increased by each stage, must not exceed the clock period. So, for example, on a typical currently available FPGA, the longest counter chain supported with a basic clock rate of 80 Megahertz, the maximum number of counter stages is about 17 or 18 stages.
Accordingly, there is a need for counter chains that may be of any length without regard to the carry-forward ripple delay.
SUMMARY OF THE INVENTION
The present invention is a synchronous counter synchronized to a master clock. The master clock may be a clock on an FPGA chip. The counter includes a first counter that increments in response to the master clock. A resynchronizer receives counter bits from the first counter and, when appropriate, generates an increment signal. A second counter, clocked by the master clock, increments in response to the increment signal. The resynchronizer is an n bit AND gate (where the first counter is an n-bit counter) that ANDs at least selected ones of the counter bits of the first counter, and a latch clocked by the master clock for latching the output of the AND gate. Thus, small counter chains are linked together using flip-flops clocked at the master clock rate, i.e., the same rate as the counter chains, to form a counter chain of any length that will function at the master clock rate. Accordingly, the present invention encompasses counter chains of unlimited size that can be implemented in a field programmable logic array (FPGA) and that can run at the maximum clock rate of the FPGA.


REFERENCES:
patent: 5559844 (1996-09-01), Lee
patent: 5943386 (1999-08-01), Chinn et al.

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