Semiconductor memory device capable of reducing power supply...

Details Semiconductor memory device capable of reducing power supply... Semiconductor memory device capable of reducing power supply...

2000-09-22

2002-10-22

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

06469952

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices capable of reducing their power supply voltage.
2. Description of the Background Art
FIG. 17
is a block diagram showing a configuration of a conventional dynamic random access memory (referred to as a DRAM hereinafter). In the figure the DRAM includes a clock generation circuit
31
, a row and column address buffer
32
, a row decoder
33
, a column decoder
34
, a memory array
35
, a sense amplifier+input/output control circuit
36
, an input buffer
37
, and an output buffer
38
.
Clock generation circuit
31
responds to external control signals/RAS and/CAS by selecting a predetermined mode of operation for general control of the DRAM.
Row and column address buffer
32
responds to external address signals A
0
to Ai (wherein i represents an integer of no less than 0) by generating row address signals RA
0
to RAi and column address signals CA
0
to CAi which are then input to row decoder
33
and column decoder
34
, respectively.
Memory array
35
includes a plurality of memory cells each storing data of one bit. Each memory cell is arranged at a predetermined address determined by a row address and a column address.
Row decoder
33
responds to row address signals RA
0
to RAi from row and column address buffer
32
by designating a row address in memory array
35
. Column decoder
34
responds to column address signals CA
0
to CAi from row and column address buffer
32
by designating a column address in memory array
35
.
Sense amplifier+input/output control circuit
36
connects a memory cell of an address designated by row decoder
33
and column decoder
34
, to one end of a data input/output line pair IOP. Data input/output line pair IOP has the other end connected to input buffer
37
and output buffer
38
. Input buffer
37
in the write mode responds to an external control signal/W by transmitting externally received data Dj (wherein j represents an integer of no less than 0) to a selected memory cell via data input/output line pair IOP. Output buffer
38
in the read mode responds to an external control signal/OE by externally outputting data read from a selected memory cell.
FIG. 18
is a circuit block diagram showing a configuration of memory array
35
and sense amplifier+input/output control circuit
36
of the
FIG. 17
DRAM, and
FIG. 19
is a circuit diagram showing in detail a configuration of one column of memory array
35
and sense amplifier+input/output control circuit
36
shown in FIG.
17
.
As shown in
FIGS. 18 and 19
, memory array
35
includes a plurality of memory cells MCs arranged in rows and columns, word lines WLs each provided for a row, and pairs of bit lines BL and /BL each provided for a column.
Each memory cell MC is connected to word line WL of a row corresponding thereto. Odd-numbered columns have their respective, multiple memory cells MCs connected to bit line BL and /BL alternately. Even-numbered columns have their respective, multiple memory cells MCs connected to bit line/BL and BL alternately.
Each memory cell MC includes an n channel MOS transistor
60
for access and a capacitor
61
for information storage. Each memory cell's n channel MOS transistor
60
has its gate connected to word line WL of a row corresponding thereto. N channel MOS transistor
60
is connected between bit line BL or /BL of a column corresponding thereto and one electrode of capacitor
61
of memory cell MC (a storage node SN). Each memory cell's capacitor
61
has the other electrode receiving a cell plate potential Vcp. Word line WL transmits an output from row decoder
33
and activates memory cell MC of a selected row. Bit line pair BL and /BL is used to input and output a data signal to and from a selected memory cell.
Sense amplifier+input/output control circuit
36
includes a column select gate
41
, a sense amplifier
42
and an equalizer
43
provided for each column. Column select gate
41
includes n channel MOS transistors
51
and
52
connected between bit lines BL and /BL and data input/output lines IO and /IO, respectively. N channel MOS transistors
51
and
52
have their respective gates connected via a column select line CSL to column decoder
34
. When column decoder
34
drives column select line CSL high or to the selected level, n channel MOS transistors
51
and
52
turn on and bit line pair BL and /BL and data input/output line pair IO and /IO are coupled together.
Sense amplifier
42
includes p channel MOS transistors
53
and
54
connected between bit lines BL and /BL and a node N
42
, and n channel MOS transistors
55
and
56
connected between bit lines BL and /BL and a node N
42
′. MOS transistors
53
and
55
have their respective gates both connected to bit line /BL, and MOS transistors
54
and
56
have their respective gates both connected to bit line BL. Nodes N
42
and
42
′ receive sense amplifier activation signals SAP and SAN, respectively, output from clock generation circuit
31
. When sense amplifier activation signals SAP and SAN are driven high and low, respectively, sense amplifier
42
responsively amplifies a slight potential difference &Dgr;V between bit lines BL and /BL to a power supply voltage Vcc.
Equalizer
43
includes an n channel MOS transistor
57
connected between bit lines BL and /BL, and n channel MOS transistors
58
and
59
connected between bit lines BL and /BL and an node N
43
′. N channel MOS transistors
57
to
59
have their respective gates all connected to node N
43
. Node N
43
receives a bit line equalization signal BLEQ and node N
43
′ receives a bit line potential VBL, which is equal to Vcc/2. When bit line equalization signal BLEQ is driven high or attains the active level, equalizer
43
responsively equalizes a potential of bit lines BL and /BL to bit line potential VBL.
The DRAM shown in
FIGS. 17
to
19
operates as described below: in the write mode, column decoder
34
allows column select signal CSL of a column corresponding to column address signals CA
0
to CAi to be driven high or attain the active level and the column's column select gate
41
conducts.
Input buffer
37
, in response to signal/W, transmits externally applied write data to bit line pair BL and /BL of the selected column via data input/output line pair IOP. The write data is provided as a potential difference between bit lines BL and /BL. Then, row decoder
33
allows word line WL of a row corresponding to row address signals RA
0
to RAi to be driven high or attain the selected level, turning on MOS transistor
60
of memory cell MC of the row. A selected memory cell's capacitor
61
stores electric charge depending on a potential of bit line BL or /BL.
In the read mode, bit line equalization signal BLEQ is initially driven low, the equalizer's n channel MOS transistors
57
to
59
turn off, and equalizing bit lines BL and /BL is stopped. Then, as shown in
FIGS. 20A
to
20
E, row decoder
33
allows word line WL of a row corresponding to row address signals RA
0
to RAi to be driven high or attain the selected level (at time t
1
). Responsively, bit lines BL and /BL has a potential slightly varying with the amount of electric charge of capacitor
61
of memory cell MC activated.
Then, sense amplifier activation signals SAN and SAP are successively driven low and high (at times t
2
and t
3
), respectively, to activate sense amplifier
42
. When bit line BL is slightly higher in potential than bit line/BL, MOS transistors
53
and
56
are reduced and thus smaller in resistance than MOS transistors
54
and
55
to pull the potential of bit line BL high and the potential of bit line/BL low. In contrast, when bit line/BL is slightly higher in potential than bit line BL, MOS transistors
54
and
55
are reduced and thus smaller in resistance than MOS transistors
53
and
56
to pull the potential of bit line/BL high and the potential of b

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