Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond
Reexamination Certificate
1999-04-14
2002-10-22
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Solder wettable contact, lead, or bond
C257S692000, C257S693000, C257S738000, C257S780000
Reexamination Certificate
active
06469393
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor package and a mount board on which the semiconductor package is mounted, and a mounting method using the same, and particularly to a technique for enhancing mount reliability of a semiconductor package having mount terminals arranged at a minute pitch.
BACKGROUND OF THE INVENTION
In order to make a further development in miniaturization, high performance and multi-functionalization of electronic equipment it is an important factor how to increase the mount density of components on a mount board. With respect to the mount of semiconductor chips, there have been proposed various CSP (Chip Size Package or Chip Scale Package) to suppress the dimension of the outer shape of a package to the same level as the dimension of the body of the semiconductor chip by improving the internal structure of the package. No standardization has been established for CSP at present, however, it is a substantially common point that all input/output terminals are formed on an element-formed surface of a semiconductor chip and the arrangement of the input/output terminals is converted to another regular area arrangement through a relay board.
As CSP is typically known a BGA (Ball Grid Array) package in which terminals arranged on a relay board are metal balls such as soldering balls, Cu balls or the like.
In the BGA package p as shown in
FIG. 1
, a semiconductor chip
27
is mounted on a principal plane of a relay board
21
and further coated with a mold resin layer
30
, and soldering balls
31
are regularly provided in an area arrangement on the other principal plane of the relay board
21
.
A first conductive pattern
22
is beforehand formed on one principal plane of the relay board
21
in association with input/output terminals
28
of the semiconductor chip
27
, and the semiconductor chip
27
is adhesively attached in a face-up style onto the relay board
21
through an insulating layer
26
of die bonding agent. The input/output terminals
28
of the semiconductor chip
27
and the first conductive pattern
22
are connected by bonding wires
29
.
The first conductive pattern
22
is electrically connected through a penetrating via hole
24
to a second conductive pattern
23
on the other principal plane side. The second conductive pattern
23
is arranged in a grid shape over the entire surface or at the peripheral portion of the other principal plane of the relay board
21
, and the soldering balls
31
are arranged on the second conductive pattern
28
.
As described above, the linear arrangement of the input/output terminals
28
along the side of the rectangular semiconductor chip
27
is finally converted through the first conductive pattern
22
, the penetrating via hole
24
and the second conductive pattern
23
to the grid arrangement of the soldering balls
31
, that is, the ball grid array.
The mount board
41
on which the BGA package p is mounted is beforehand provided with lands
42
correspondingly to the arrangement of the soldering balls
31
on one principal plane. For example, preliminary solder is coated on the lands
42
, and the soldering balls
31
of the BGA package p and the lands
42
of the mount board
41
are positioned to each other and joined to each other by a reflow soldering method or the like.
As shown in
FIG. 1
, the respective adjacent ones of the second conductive pattern
23
on the relay board and the respective adjacent ones of the lands
42
on the mount board
41
are mutually insulated from each other by the soldering resist layer
25
and
43
in order to avoid the adjacent ones from being short-circuited by bridges of solder.
The opening edges
25
a
and
43
a
of the soldering resist layers
25
and
43
are formed on the second conductive pattern
23
and the lands
42
, respectively. That is, the respective opening areas of the soldering resist layers
25
and
43
are set to be smaller than the respective areas of the surfaces of the second conductive pattern
23
and the lands
42
.
This is an idea to minimize the effect of dispersion of coplanarity (uniformity in height) of the soldering balls
31
on the mount reliability and to make the height of the balls uniform irrespective of presence or absence of a wire pattern at the periphery of lands.
Such the forming style of the lands and the solder resist layers as described above is hereinafter referred to as “throttle resist type”.
If it is promoted in the future to further reduce the arrangement pitch of the soldering balls
31
, however, in order to suppress the enlargement of the BGA package p due to increase of the number of the terminals of the semiconductor chip
27
, the dimension of the second conductive pattern
23
and the soldering balls
31
themselves must be reduced so that the joint area between the second conductive pattern
23
and the soldering balls
31
is reduced. When such a BGA package p is mounted on the mount board and a predetermined temperature cycle test is performed, stress due to thermal deformation of the mount board
41
is concentrated onto the interface between the second conductive pattern
23
and the soldering balls
31
, and the occurrence frequency of cracks (cracks) at this portion rises up. In addition, as the arrangement pitch of the soldering balls
31
is reduced, the risk that cracks occur in a large number of soldering balls
31
at the same time is increased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor package and a mount board which can beforehand prevent the above disadvantage and enhance the mount reliability and a mounting method using the same.
As a result of repeated considerations to attain the above object, the inventor has found out that if lands are wholly exposed from a solder resist layer at least at one of a semiconductor package side and a mount board side to thereby enable a conductive material layer formed of soldering or the like to extend to the side wall surfaces of the lands, the joint strength between the conductive material layer and the lands can be improved by the increasing contact area between the conductive material layer and the lands and a shape of the conductive material layer.
In the semiconductor package of the present invention, a land of the package-side is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface of the land.
Further, in the mount board of the present invention, a land of the board-side is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface of the land.
Further, in the mounting method of the present invention, at least one of a package-side land and a board-side land is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface thereof, and the package-side land and the board-side land are electrically connected to each other through a conductive material layer.
REFERENCES:
patent: 5462837 (1995-10-01), Yamaguchi
patent: 5636104 (1997-06-01), Oh
patent: 5726501 (1998-03-01), Matsubara
patent: 5844782 (1998-12-01), Fukasawa
patent: 5973931 (1999-10-01), Fukasawa
patent: 6011312 (2000-01-01), Nakazawa et al.
patent: 6060775 (2000-05-01), Ano
patent: 6084300 (2000-07-01), Oka
patent: 0 776 150 (1997-05-01), None
patent: 11-121688 (1999-04-01), None
patent: WO 90 07792 (1990-07-01), None
Patent Abstracts of Japan vol. 1996, No. 11, Nov. 29, 1996 & JP 08 172143 A (Sony Corp), Jul. 2, 1996.
Frommer William S.
Frommer & Lawrence & Haug LLP
Ryan Matthew K.
Sony Corporation
Wilson Allan R.
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