Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-04-05
2002-10-29
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000, C257S685000
Reexamination Certificate
active
06472735
ABSTRACT:
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
The present invention relates generally to chip stacks, and more particularly to a chip stack which employs the use of an anisotropic epoxy as an alternative to solder to facilitate the interconnection of the various components of the chip stack.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as
3
D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the “footprint” typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant's U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The chip stack disclosed in the parent application provides yet a further alternative arrangement and technique for forming a volumetrically efficient chip stack. In such chip stack, connections are routed from the bottom of the chip stack to the perimeter thereof so that interconnections can be made vertically which allows multiple integrated circuit chips such as BGA, CSP, fine pitch BGA, or flip chip devices to be stacked in a manner providing the potential for significant increases in the production rate of the chip stack and resultant reductions in the cost thereof.
In the above-described chip stacks, solder is the interconnect medium used to form the various interconnections between the components of the chip stacks. The current trend in electronics is for more functionality in a small device. This generally means more I/O's in a smaller package. Interconnecting these smaller devices in turn requires a denser circuit board or other interconnection scheme. As the dimensions become smaller, the use of solder as the interconnect medium becomes increasingly less attractive. In this respect, smaller sizes require tighter control over such variables as solder paste and deposition, part geometries, reflow temperatures, etc. In these smaller devices, occurrences of solder bridging between neighboring interconnects becomes more common and difficult to control. Additionally, the smaller dimensions make post assembly cleaning very difficult. With regard to such cleaning, CFC's are no longer allowed, with water washable flux being difficult to remove in small cavities due to the high surface tension of water. Either no-clean flux must be used or the chip stack assembly must be designed with cleaning objectives in mind.
In the assembly of chip stacks, the interest in lead-free solders is increasing and eventually will be required in Asia, Europe, and the United States. The most promising substitutes for tin/lead solder are based on tin-silver-copper-bismuth combinations which have melting points in excess of 200° C. These melting points are substantially higher than traditional tin/lead solders, which melt at approximately 180° C. These elevated melting points will require higher soldering temperatures. For packaged chip and flip chip assemblies, the higher melting points of lead-free solders may prove to be a concern, since these devices may not be able to withstand repeated elevated reflow temperatures. Further, the higher temperatures negate the use of a high temperature solder for subassemblies combined with a low temperature solder for attachment to a mother board.
The use of solder as an interconnect medium creates further challenges in relation to the three-dimensional stacking of devices. The rework of a stacked assembly becomes difficult, tedious, and labor intensive. Accordingly, the first pass yield must be high. Solder bridging or solder opens cannot be tolerated in such chip stacks.
The present invention eliminates many of the problems and challenges arising as a result of the use of solder as the interconnect medium by providing a chip stack and method of stacking integrated circuit (IC) devices using an anisotropic epoxy for the interconnections between the layers as an alternative to solder. Anisotropic epoxy consists of a fast cure epoxy containing small conductive particles uniformly dispersed within the epoxy component of the material. The density of particles is limited to the amount that does not cause contact from particle to particle. The epoxy may be in the form of a liquid or film. Typically, gold plated nickel particles of uniform size anywhere from five to ten microns in diameter are used. The liquid is dispensed or film placed between opposing conductive pads, with heat and pressure thereafter being applied. With pressure, particles are trapped between the conductive pads, thus forming a conductive conduit between the pads. The heat then cures the epoxy which holds the structure (i.e., layers) together. If the pads are nickel/gold plated, the particles form a pressure contact between the pads. If the pads are plated with a tin based metal and sufficient heat is applied, the particles form a metallugical connection between the pads. By controlling the size of the particles, bridging between adjacent pads can be eliminated, thus allowing for the achievement of fine pitch between the pads. Since flux is not used, post assembly cleaning is not required. Also, the composition of the particles does not include any toxic metal such as lead.
The processing window associated with the use of an anisotropic epoxy as the interconnect medium in the chip stack is very tolerant, with process temperatures being below 200° C. Once cured, the anisotropic epoxy does not reflow at temperatures above 200° C. Chip stacks assembled through the use of the anisotropic epoxy can be easily made using a panel format, then separating the stacks using standard PCB routing procedures. For example, typical panels 4 inches by 5½ inches with multiple stack sites (16 or more on a panel)may be processed then stacked in a stacking fixture, and cured with heat and pressure as provided by a lamination press. The panels can easily be designed with multiple devices per layer for each resultant chip stack. Multiple devices such as BGA's, TSOP's, or bare die can be intermixed and placed on one base substrate. All interconnects between devices
Clark Jasmine J B
Stetina Brunda Garred & Brucker
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