Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
2000-08-24
2002-10-22
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C331S025000, C331S016000, C327S156000, C327S159000
Reexamination Certificate
active
06469583
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a PLL (Phase Locked Loop) control circuit for digital oscillation frequency control and a control method adopted in the same.
In such communication units as heterodyne receivers, particularly portable telephone sets, a local oscillator executes a mixing operation to obtain an intermediate frequency signal having a fixed frequency difference from a desired received signal frequency. Also, the intermediate frequency signal thus obtained is amplified in a high grain intermediate frequency amplifier to realize high reception sensitivity. To this end, a PLL is often used as local oscillator.
FIG. 5
is a block diagram showing a prior art example of PLL control circuit, and
FIG. 10
shows the frame timing of al usual digital portable telephone set. As shown in
FIG. 10
, in the digital portable telephone set a reception channel, peripheral channels and a transmission channel are switched one over to another in a fixed cycle. In this case, the PLL output frequency should also be switched.
In this case, the PLL output frequency should be pulled in a short period of time at the time of the frequency switching. The prior art PLL control circuit will now be described with reference to
FIG. 5
by assuming PLL output frequency to be, for instance:
680 MHz at the reception channel time,
690 MHz at the peripheral channel time and
740 MHz at the transmission channel time.
The PLL circuit shown in
FIG. 5
is a typical one comprising a reference frequency oscillator
101
, a voltage controlled oscillator (VCO)
102
, variable frequency dividers
104
and
105
for frequency dividing the outputs of the two oscillators
101
and
102
, respectively, a phase comparator
108
for phase comparing the outputs of the two variable frequency dividers
104
and
105
, a charge pump
107
connected to the output side of the phase comparator
106
, and a low-pass filter
103
for filtering the output of the charge pump
107
and feeding back the filtered output to the VCO
102
. The above component constitutes a typical PLL. The PLL control circuit further comprises a serial-to-parallel (S/P) converter
110
for controlling the variable frequency dividers
104
and
105
, a parallel-to-serial (P/S) converter
111
for controlling the S/P converter
110
, a timer circuit
112
and a central processing unit (CPU)
113
. The individual circuit components noted above are well known to one skilled in the art, and they will not be described here.
The reference frequency of the reference frequency oscillator
101
is assumed to be 14.4 MHz. Then, when the output frequency of the VCO
102
is set to 680 MHZ at the reception channel time:
the phase comparison frequency of the phase comparator
106
is 200 kHz;
the frequency division number of the variable frequency divider
104
is 14.4 MHz/200 kHz=72; and
the frequency division number of the variable frequency divider
105
is 680 MHz/200 kHz=3,400.
When the output frequency of the VCO
102
is set to 690 MHz at the peripheral channel time:
the phase comparison frequency of the phase comparator
106
is 200 kHz;
the frequency division number of the variable frequency divider
104
is 14.4 MHz/200 kHz=72; and
the frequency division number of the variable frequency divider
105
is 690 MHZ/200 kHz=3.450.
When the output frequency of the VCO
102
is set to 740 MHz at the transmission channel time:
the phase comparison frequency of the phase comparator
106
is 160 MHz;
the frequency division number of the variable frequency divider
164
is 14.4 HMz/160 kHz=90; and
the frequency division raito of the variable frequency divider
104
is 740 MHz/160 kHz=4,625.
The operation in the case of sequentially designating the above settings in a time schedule as shown in
FIG. 10
, will now be described with reference to the flow chart of
FIG. 7
, i.e., the flow chart of control routine in the CPU
113
shown in FIG.
5
.
FIG. 6
shows the format of serial data. The serial data consist of data “D
00
” to “D
16
”, and designate the frequency division. number of the variable frequency dividers
104
and
105
in the form of binary numbers.
Referring to the flow chart of
FIG. 7
, in a step S
1
the CPU
113
waits for an interruption from the timer circuit
112
. When receiving an interruption from the timer circuit
112
, the CPU determines the kind of the interruption. Specifically, in a step S
2
the CPU checks whether the kind of the interruption is “A”. When the kind is “A”, the CPU executes steps S
3
to S
5
. More specifically, when the kind is “A”, corresponding to the frequency setting at the reception channel time, the CPU sets the frequency division number of the variable frequency divider
104
by using the format of “D
00
”=“0” in
FIG. 6
(step S
3
). Then, the CPU waits for completion of the serial output from the P/S converter
111
(step S
4
). Then, the CPU sets the frequency division number of the variable frequency divider
105
by using the format of “D
00
”=“1” in
FIG. 6
(step S
5
).
When it is not determined in the step S
2
that the kind of interruption is “A”, the CPU executes a step S
6
of checking whether the kind of interruption is “B”. When it is determined in the step S
6
that the kind of interruption is “B”, the CPU executes steps S
7
to S
9
for frequency setting at the peripheral channel time shown in FIG.
10
. More specifically, in the step S
7
the CPU sets the frequency division number of the variable frequency divider
104
by using the format of “D
00
”=“0”. Then, in the step S
8
the CPU waits for completion of the serial output of the P/S converter
111
. Then, in the step S
9
the CPU sets the frequency division number for the variable frequency divider
105
by using the format of “D
00
”=“1”.
Finally, when it is not determined in the step S
6
that the kind of interruption is “B”, the CPU executes step S
10
to check whether the kind of interruption is “C”. When the kind is “C”, the CPU executes steps S
11
to S
13
for frequency setting at the transmission channel time shown in FIG.
10
. More specifically, in the step S
11
the CPU sets the frequency division number of the variable frequency divider
104
by using the format of “D
00
”=“0”. Then, in the step S
12
the CPU waits for completion of the serial output of the P/S converter
111
. Subsequently, in the step S
13
the CPU sets the frequency division number for the variable frequency divider
105
by using the format of “D
00
”=“1” in FIG.
6
.
Problems arising in the above prior art technique will now be described in connection with a case of frequency switching from the transmission channel to the reception channel.
At the transmission channel time, the frequency division number of the variable frequency divider
104
is set to 90, so that the output frequency thereof is 14.4 MHz/90=160 kHz. The frequency division number of the variable frequency divider
105
is set to 4,625, and the PLL is controlled to make the output frequency of the variable frequency divider
104
equal to the output frequency (160 kHz) of the variable frequency divider
104
. The frequency of the VCO
102
is 160 kHZ×4,625=740 MHz.
For frequency switching to the reception channel frequency, the frequency division number of the variable frequency divider
104
is set to 72 so that the output frequency thereto is 14.4 MHz/72=200 kHz. At this time, the frequency division number of the variable frequency divider
105
remains at 4,625, and the PLL circuit is controlled such that its output frequency approaches 200 kHz×4,625=925 MHz. Subsequently, the frequency division number of the variable frequency divider
105
is set to 3,400. At this time and only at this time the PLL circuit is controlled to make the output frequency of the VCO 102 to be 200 kHz×3,400=68 MHz.
In the above process of switching the output frequency of the PLL: circuit, by switching the frequency from 740 MHz to 680 MHz, the freq
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