Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2001-04-17
2002-10-01
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S106000, C438S118000, C438S123000
Reexamination Certificate
active
06458625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor packaging and, more particularly, to a method and apparatus for providing multi-chip chip semiconductor device (die) packages.
2. Statement of the Art
Integrated circuit devices proceed through a complicated and time-consuming fabrication routine before being completed and ready for packaging. Once this integrated circuit device passes final inspection for acceptability, it is passed to packaging. The integrated circuit device (IC) then is typically encapsulated in a protective package made of plastic, metal, ceramic material, or combinations thereof. The package is sealed to insulate the semiconductor die from the effects of temperature extremes, humidity and unintentional electrical contacts. The package has a plurality of conductive leads protruding from the encapsulation material for connecting to external devices on a printed circuit board. Various types of semiconductor packages include sealed metal cans, plastic and ceramic dual in-line packages, small outlining packages, single in-line packages, surface mount packages, and various other flat packages.
One type of semiconductor device assembly is a lead-on-chip (LOC) assembly as shown in the prior art drawing FIG.
1
. In drawing
FIG. 1
, a strip
10
of lead frames
12
is provided. Located in a center portion of each lead frame
12
is a semiconductor die
14
attached to the lead fingers
16
, typically by way of wire bonds. An example of a single semiconductor die
14
being attached to a lead frame
12
is shown in prior art drawing FIG.
2
. The wire bonds
18
connect the semiconductor die
14
to the lead fingers
16
of the lead frame
12
. Next, the lead fingers
16
are trimmed and an encapsulant material is applied over the semiconductor die
14
and portions of lead fingers
16
to completely encapsulate and seal wire bonds
18
, portions of lead fingers
16
, and semiconductor die
14
, making a single chip package.
There is a need to increase the semiconductor die density of a semiconductor package to include two or more semiconductor dice in one package. A high density package having multiple semiconductor dice therein increases the electronic component density on a printed circuit board. Such a high density semiconductor package also maximizes space utilization on a printed circuit board and further increases the number of active elements on the printed circuit board. U.S. Pat. No. 5,483,024, entitled “High Density Semiconductor Package,” issued Jan. 9, 1996, discloses a high density semiconductor package, an example of which is depicted in the prior art drawing FIG.
3
. In the '024 Patent, two semiconductor dice
14
are fixed on the lead fingers
16
of a corresponding one of two lead frames
12
. The semiconductor dice
14
and the lead frames
12
are then encapsulated (not shown) wherein a portion of the lead frames protrude and extend from the package. Wire bonds
18
electrically connect each semiconductor die
14
to its respective lead frame
12
. An adhesive material
20
is used to bond the back surfaces of semiconductor dice
14
to one another. The high density semiconductor package illustrated in the '024 Patent does achieve a multi-chip package, but there are shortcomings in the manufacture of the same.
One problem is that a first semiconductor die must be attached to its lead frame and then electrically connected with the wire bonds
18
. The two or more semiconductor dice
14
are adhered one to another. Once they are attached, the semiconductor dice
14
must be carried in an open basket that does not provide great rigidity that otherwise leads to poor wire bonding during the wire bonding process. A strong base support is necessary in order to provide a wire bond application that does not have weaknesses that lead to subsequent electrical or mechanical failure.
Another disadvantage with the '024 Patent disclosure is that the semiconductor device assembly must be flipped in order to do the wire bonding on the second surface. This exposes the delicate wire bonds on the first surface of the first semiconductor die to risks of detachment that may occur due to the stressing that results while wire bonding the second surface of the second semiconductor die as the assembly is held in a less than desirable open support structure. Thus, it would be desirable to be able to use a wire bonding process where the wire bonds are made between both the first semiconductor die and the second semiconductor die and their respective lead frames from the same access point.
Other types of multiple chip modules have been developed in the prior art. Another example is shown in U.S. Pat. No. 5,422,435, entitled “Stacked Multi Chip Modules and Method of Manufacturing,” issued Jun. 6, 1995. The '435 Patent discloses a circuit assembly that includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. The multiple semiconductor dice are stacked one on top another or adjacent one another in a tandem position and then are electrically connected using wire bonds to a lead frame attached to a base substrate. The '435 Patent allows the wire bonding between multiple semiconductor dice to be performed during the same operation, but the use of a very complicated substrate with a lead frame assembly requires a larger semiconductor die than otherwise desired as well as a much more complicated assembly process of attaching the semiconductor devices and any other intervening elements in a stack arrangement to the carrier substrate that includes the lead frame. No lead fingers of the lead frame are directly connected to the semiconductor die, such as in the '024 Patent previously described. Thus, the '435 Patent does not have the same advantages as using a lead-on-chip configuration as is achieved in the '024 Patent.
Another multi-chip stacked device arrangement is depicted in U.S. Pat. No. 5,291,061, entitled “Multi Chip Stacked Devices,” issued Mar. 1, 1994, and commonly assigned with the present invention. The '061 Patent discloses multiple stacked die devices attached to a main substrate. Each stacked semiconductor die device is then electrically connected using wire bonds to a separate lead frame, which is not attached to the main substrate. The '061 Patent suffers from the same problem previously described in that it is not easily assembled using the improved lead-on-chip lead frame and the devices are stacked one on top another so as to make wire bonding difficult or done in stages after the addition of each subsequent die device.
SUMMARY OF THE INVENTION
The present invention is directed to a multi-chip semiconductor device package using a lead-on-chip lead frame configuration. The lead-on-chip multi-chip semiconductor device package places two or more lead-on-chip semiconductor dice into one package that are either attached to their own lead-on-chip lead frame or are mounted to the same lead-on-chip lead frame and subsequently wire bonded to provide electrical connection from the dice to the lead frame while in substantially the same arrangement without requiring the assembly of the multiple semiconductor dice and lead frame to be flipped for additional wire bonding attachment of the dice to the lead frame.
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Micro)n Technology, Inc.
Smith Brad
TraskBritt
Zarabian Amir
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