Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Specified wide band gap semiconductor material other than... – Diamond or silicon carbide

Reexamination Certificate

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C257S289000, C257S369000, C257S371000

Reexamination Certificate

active

06472685

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a field effect transistor, and more particularly relates to an improved semiconductor device in which the mobility of carriers is increased by applying a tensile strain to a channel layer where carriers are moving.
Currently, the majority of transistors formed on a silicon substrate are metal-insulator-semiconductor (MIS) field effect transistors. Methods for enhancing the performance characteristics of an MIS transistor by applying a tensile strain to an Si channel layer were reported by J. Welser et al. in “Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs”, IEDM Tech. Dig. 1994, p. 373, and by K. Rim et al. in “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs”, IEDM Tech. Dig. 1995, p. 517.
FIG. 16
is a cross-sectional view illustrating a basic structure of a semiconductor region in a field effect transistor formed by these methods. As shown in
FIG. 16
, the semiconductor region basically includes: an SiGe buffer layer
101
, in which the content of Ge linearly increases from 0 to x; an Si
l-x
Ge
x
layer
102
, the lattice strain of which has been relaxed; and an Si layer
103
, which has received a tensile strain. These layers are stacked in this order on a silicon substrate
100
. In this structure, the lattice strain of the Si
l-x
Ge, layer
102
, formed on the SiGe buffer layer
101
, is relaxed such that the lattice constant of the Si
l-x
Ge
x
layer
102
increases to match with that of the non-strained SiGe layer
101
. And a tensile strain is applied to the Si layer
103
grown thereon.
FIG.
17
(
a
) is a crystal structure diagram illustrating the lattice states of an Si
l-x
Ge
x
layer and an Si layer before these layers are stacked one upon the other. FIG.
17
(
b
) is a crystal structure diagram illustrating a state where the Si layer has received a tensile strain after these layers have been stacked. And FIG.
17
(
c
) is a band diagram illustrating a heterojunction structure consisting of the Si
l-x
Ge
x
layer and the Si layer. As shown in FIG.
17
(
a
), the lattice constant of Si crystals is smaller than that of Si
l-x
Ge
x
crystals. Thus, if the Si layer is epitaxially grown on the Si
l-x
Ge
x
layer, the Si layer receives a tensile strain from the Si
l-x
Ge
x
layer as shown in FIG.
17
(
b
). As a result, the energy band of the heterojunction structure consisting of the Si
l-x
Ge
x
layer and the Si layer, which has received the tensile strain, is as shown in FIG.
17
(
c
). Specifically, since the Si layer has received a tensile strain, the sixfold degeneracy is dissolved in the conduction band, which is split into a twofold degenerate band &Dgr;(
2
) and a fourfold degenerate band &Dgr;(
4
). On the other hand, the twofold degeneracy is also dissolved in the valence band, which is split into a light-hole band LH and a heavy-hole band HH.
That is to say, in such a heterojunction structure, the edge of the conduction band in the Si layer
103
shown in
FIG. 16
is the twofold degenerate band &Dgr;(
2
), and has smaller energy than that of electrons in the Si
l-x
Ge
x
layer
102
. Thus, if a field effect transistor is formed by using the Si layer
103
as a channel, then electrons, having a smaller effective mass in the band &Dgr;(
2
), move through the channel. As a result, the horizontal mobility of electrons increases in the Si layer
103
and the operating speed of the transistor also increases. In addition, the energy level of the band &Dgr;(
2
) is lower than that at the edge of the conduction band in the Si
l-x
Ge
x
layer
102
. Thus, if the Si layer
103
is used as a channel, electrons can be confined in the Si layer by utilizing a heterobarrier formed between the Si and Si
l-x
Ge
x
layers.
On the other hand, the edge of the valence band of the Si layer
103
is a band of light holes having a smaller effective mass, which have smaller energy than that of holes in the Si
l-x
Ge
x
layer
102
. Thus, if such an Si layer
103
is used as a channel region for a p-channel transistor, then the light holes, having a smaller effective mass, horizontally move in the Si layer
103
. As a result, the mobility of holes increases and the operating speed of the transistor also increases.
As reported, in both n- and p-channel field effect transistors, the performance characteristics thereof can be enhanced by using an Si layer
103
, which has received a tensile strain, as a channel region.
However, these field effect transistors, formed by the conventional methods, have the following problems.
Firstly, in order to apply a tensile strain to the Si layer
103
functioning as a channel region, the SiGe buffer layer
101
should be grown on the silicon substrate
100
until the layer
103
becomes thick enough to reduce the lattice strain of the Si
l-x
Ge
x
layer
102
. However, when the lattice strain of the Si
l-x
Ge
x
layer
102
is relaxed, a large number of dislocation are generated in the SiGe buffer layer
101
. A great number of dislocations are also present in the Si layer
103
formed on the Si
l-x
Ge
x
layer
102
. The dislocations such as these not only deteriorate the performance characteristics of the transistor, but also seriously affect the long-term reliability thereof. For example, it was reported that the dislocations could be reduced by modifying the structure of the SiGe buffer layer. However, in accordance with current techniques, the density of dislocations cannot be reduced to lower than about 10
5
cm
−2
. Such a device must be said to have very many defects.
Secondly, the buffer layer, provided for reducing the lattice strain, should be formed sufficiently thick (e.g., 1 &mgr;m or more). Thus, it takes a great deal of time to form such a layer by crystal growth. In view of the throughput of a device, such a structure is far from fully practical.
Thirdly, in the conventional structure, the energy level at the edge of the valence band in the Si layer
103
is lower than the energy level at the edge of the valence band in the Si
l-x
Ge
x
layer
102
. Thus, a heterobarrier, where the Si
l-x
Ge
x
layer
102
is located at a higher level, is formed, and it cannot be expected that holes, having a smaller effective mass, are confined in the Si layer
103
.
SUMMARY OF THE INVENTION
In view of these problems, the present invention was made to provide a sufficiently reliable, high-performance transistor by applying a tensile strain to a channel layer mainly composed of silicon, without providing any thick buffer layer for reducing a lattice strain, in which a large number of dislocations exist.
The semiconductor device of the present invention includes a field effect transistor on a substrate. The field effect transistor includes: a first silicon layer formed on the substrate; a second silicon layer, which is formed on the first silicon layer, contains carbon and has received a tensile strain from the first silicon layer; and a gate electrode formed over the second silicon layer. The second silicon layer functions as a channel region of the field effect transistor.
In this semiconductor device, since carbon, having a smaller atomic diameter than that of silicon, is contained in the second silicon layer, the lattice constant of the second silicon layer is smaller than that of the first silicon layer. Accordingly, even if no thick buffer layer is provided between the first and second silicon layers, the second silicon layer containing carbon receives a tensile strain from the first silicon layer. As a result, in the second silicon layer, the sixfold degeneracy is dissolved in the conduction band, which is split into a twofold degenerate band and a fourfold degenerate band. The edge of the conduction band in the channel region formed out of the second silicon layer is the twofold degenerate band. The effective mass of twofold degenerate electrons is smaller than that of electrons in the first silicon layer. Thus, if current is horizontally supplied, the effective mass of electrons decreases on the pl

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