Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-10-01
2002-12-03
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185220
Reexamination Certificate
active
06490195
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a non-volatile memory cell which can be electrically erased and written; and, more particularly, the invention relates to a non-volatile semimconductor storage device, such as a flash memory, in which a threshold voltage associated with multiple-valued information comprising four values or more can be programmed in one memory cell and to a method for changing a threshold of a non-volatile cell memory. For example, the invention relates to a technique which is effectively used in a data processing system, such as a file memory system utilizing such a non-volatile semiconductor storage device.
Non-volatile semiconductor storage devices, e.g., flash memories, have been provided which can store imfor-mation through injection and extraction of electrons to and from a floating gate. A flash memory includes a memory cell transistor having a floating gate, a control gate, a source and a drain. The threshold voltage of such a memory cell transistor increases as electrons are injected into the floating gate and decreases as electrons are extracted from the floating gate. The memory cell transistor stores information that depends on whether the threshold voltage is higher or lower than a word line voltage (a voltage applied to the control gate) for data readout. In this specification, a state in which the threshold voltage is lower is referred to as an “erase state” and a state in which it higher is referred to as a “write state”, although this is not a limitation of the invention.
There are flash memories of this type in which information comprising four or more values is stored in one memory cell transistor. An example of articles that describe such multiple-valued memories appears on pages 48 and 49 of “Nikkei Microdevice” (November, 1994 issue). Another example is Japanese Patent Laid-Open No. 297996/1997.
SUMMARY OF THE INVENTION
In a multiple-valued memory, for example, information comprising four values can be stored in one memory cell transistor by allowing selection of one state from among an erase state and first, second and third write states whose threshold voltages relative to that of the erase state are different from each other. When an erase operation precedes a write operation, information comprising four values can be stored by selecting none of the first, second and third write states or selecting any one of the write states. During a write operation for this purpose, write control information is necessary to determine whether to select a write operation to achieve one of the first, second or third write states. Such write control information can be maintained using a sense latch circuit and a data latch circuit provided for each bit line.
For example, the sense latch circuit comprises a static latch; one end of a bit line is connected to each of a pair of input and output terminals of the sense latch circuit; and the drain of the memory cell transistor is connected to each bit line. Further, the data latch circuit is connected to the other end of each bit line. The sense latch circuit senses whether a current flows or not between the source and drain of the memory cell transistor when a read voltage or a verify voltage is applied to the control gate of the same. Bit lines at the non-operation selection side of the sense-latch circuit are precharged at a reference level. When a high potential difference is formed between the control gate and the drain, it is possible to identify whether each memory cell is selected or not for writing by increasing or decreasing the drain voltage of the memory cell. In this case, the sense latch circuit latches data depending on the whether a write operation is selected or not. This latch data is the write control information described above.
Such write control information is generated by a data conversion circuit for every two bits of write data supplied externally and is latched in the sense latch circuits for bit lines selected to be written and the data latch circuits for each of the pairs of bit lines that share the sense latch circuit. When a write operation is performed on each word line, write control information is latched in advance in the sense latch circuits and data latch circuits for all bit lines that share the word line.
During a write operation, it is first determined whether the first write state is present or not according to write control information latched in a sense latch circuit. Next, it is determined whether the second write state is present or not according to write control information transferred internally from one of the data latch circuits to the sense latch circuit. Further, it is determined whether the third write state is present or not according to write control information transferred internally from the other data latch circuit to the sense latch circuit. Thus, four-valued information identified by two bits of data can be stored in one memory cell. During the write operation in the first, second and third write states described above, a verify operation is performed to check whether a threshold voltage assigned to each of the write states has been reached or not.
At this time, some memory cells may be overwritten relative to the first, second or third write state, and, in an overwrite state, the threshold voltage may not be distinguished from other write states. For example, the threshold voltage of a memory cell which should be in the first write state can be increased to a level at which it can not be distinguished from the threshold voltage in the second write state. In such a case, the write operation is redone from the beginning by performing the write operation again after performing an erase operation on the memory cells which are to be written.
However, once a write operation is performed in the first, second or third write state, the write control information latched in the sense latch circuit is overwritten and erased by another piece of write control information transferred internally from a data latch circuit. Therefore, in order to perform a rewrite operation attributable to overwrite, the same write data must be received from the outside again. For this reason, a control circuit that controls access to a flash memory must maintain write data in a work memory or the like for a certain period of time after the write operation to the flash memory. The inventors have discovered that this increases the burdens associated with the control over access to a flash memory and can therefore reduce the efficiency of flash memory access or data processing.
The above-described situation similarly occurs in the case of additional writing. For example, a flash memory is used for a file memory system or the like which is compatible with a file system based on a magnetic disc storage device, such as a hard disc device. In this case, a part of the storage area of a flash memory is assigned to a management area which is separate from a user area. In a flash memory that accommodates write and erase on a word line basis, memory cells for one word line (hereinafter simply referred to as “sector”) are assigned to a user area and a management area, and the management area stores information on the validity of the user area of the associated sector and information on the number of rewrites. It may be required to perform the storage of such information separately from the rewrite of user data in a sector because of the nature of the information. Additional writing is a mode of a write operation that can meet such a requirement.
In the case of an additional write operation, additional write data is supplied to memory cells selected for writing. Since the write operation is performed sector by sector, it is necessary to save the data in memory cells which are unselected for writing, and both of the saved data and the additional write data must be written in the write operation.
However, the write operation must be redone from the beginning also in this case if an overwrite state or the like occurs. In doing so, if data for r
Harada Toshinori
Kanamitsu Michitaro
Kotani Hiroaki
Kubono Shoji
Nozoe Atsushi
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