Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-03-19
2002-12-03
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185190
Reexamination Certificate
active
06490201
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile memory and a method of non-volatile memory programming, and more particularly to a technique that can be effectively utilized for a write verifying operation in a flash memory or the like wherein electrical write erasion is made possible.
A non-volatile memory cell, such as a flash EEPROM (hereinafter to be referred to merely as “flash memory”), as illustrated in
FIG. 24
, has a diffusion layer comprising a source and a drain and a stacked structure into which a floating gate and a control gate are configured over a semiconductor substrate between the source and the drain via a gate insulating film, wherein the control gate is connected to a word line, the drain, to a bit line (or a data line), the source, to a source line. The write operation can be broadly classified into an FN (Fowler Nordheim) tunnel write type by which a high voltage, such as 18.1 V, is applied to the control gate and an electron FN tunnel current is let flow from a channel to the floating gate via the gate insulating film to accumulate electric charges, and a channel hot electron type by which hot electrons generated by a current flowing between the source and the drain are accumulated at the floating gate.
The present inventors earlier developed a multi-value type flash memory. In this multi-value memory, it is necessary to make four threshold voltage (hereinafter to be abbreviated to Vth) distributions matching two bits (four values) each of memory cells. In doing so, processing for band narrowing to write each distribution in a certain separate range is required to ensure reliability of data conservation. In order to accomplish such write operations for such band narrowing, write operations and verify operations are carried out with write pulses (PULSE 1 through 5 . . . ) which are intended to make the variant &Dgr; Vth of the threshold voltage per write operation smaller than the difference between the threshold voltages as shown in
FIG. 25
, so that the Vth of the memory cell reach the desired threshold voltage range by a plurality each of write operation and verify operations.
Incidentally, a search after the accomplishment of the invention under the present application revealed that examples of floating memory in which the voltage of the write pulses is raised stepwise or the pulse width increased are found in the Japanese Published Unexamined Patent Application No. Hei 9(1997)-55092, the Japanese Published Unexamined Patent Application No. Hei 7(1995)-73685 (U.S. Pat. No. 5,467,309) and the Japanese Published Unexamined Patent Application No. Hei 3(1991)-130995 (U.S. patent application Ser. No. 89/367,597). However, none of these examples of the prior art makes any mention of the presence of memory cells which deviate from their inherent characteristics and are suddenly excessively written into, as will be described below.
In designing the Vth distributions, margins are allowed for various coefficients of dependence (including Vcc, temperature, write characteristics, erase characteristics and deterioration due to rewriting). However, there are memory cells which, as rewriting into them is repeated, deviate from their inherent characteristics and are suddenly excessively written into. In the present application, such memory cells will be referred to as erratically written memory cells, or simply erratic cells, because they may return to their original characteristics after erasion following such sudden excess writing and this phenomenon is not highly reproducible. Such erratic cells require erasion of the excessively written state and rewriting and, if the rewriting into some sectors can be done normally, those sectors will be considered good ones or, if not, they will be treated as faulty sectors thereafter.
Such erratic cells, because of the low reproducibility, may return to normalcy after only one round of erasion, or may not even after repeated writing and erasion. Therefore, it seems most rational, with the duration of writing and the frequency of fault occurrence taken into account, to regard the sectors which permit normal writing after a single round of erasion as being good ones and those which do not as faulty sectors and to write the same data into other sectors. However, even if the sectors permitting normal writing after a single round of erasion are regarded as being good ones, an increase in the duration of writing is unavoidable, and disqualifying those that require two or more rounds of erasion would result in an increased frequency of fault occurrence. Relief by rewriting into another sector after determining a faulty sector or sectors would involve the problem of increasing the burden on the user and corresponding inconvenience.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a non-volatile memory and a method of non-volatile memory programming realizing stable write operations. Another object of the invention is to provide a non-volatile memory and a method of non-volatile memory programming reduced in the frequency of fault occurrence and improved in the convenience of use while shortening the substantial length of time required for writing. These and other objects and novel features of the invention will become more apparent for the following description in this specification when taken in conjunction with the accompanying drawings.
To briefly describe a typical aspect of the invention disclosed in this application, there is provided a non-volatile memory having a plurality of word lines, a plurality of bit lines and a plurality of memory elements having stored information corresponding to electric charges accumulated at floating gates at the intersections of the plurality of word lines and the plurality of bit lines, and electrically performing operations to write and erase the stored information, wherein a write control circuit for controlling the electric charges accumulated at the floating gates by performing a verify operation, after performing a write operation in a prescribed write quantity on the memory elements, carries out one or more each of search write operations, set to a smaller write quantity than the prescribed write quantity at the time of start of writing, and verify operations matching thereto.
To briefly describe another typical aspect of the invention disclosed in this application, there is provided a method of non-volatile memory programming for non-volatile memories each having a plurality of word lines, a plurality of bit lines and a plurality of memory elements having stored information corresponding to electric charges accumulated at floating gates at the intersections of the plurality of word lines and the plurality of bit lines, and electrically performing operations to write and erase the stored information, whereby one or more each of search write operations, set to a smaller write quantity than a prescribed write quantity at the time of start of writing, and verify operations matching thereto are performed, write operation control is so set as to perform a write operation set to the prescribed write quantity and a verify operation matching thereto after the plurality each of search write operations and verify operations, and the write operation is ended if it is so determined that the verify operation has caused a threshold voltage matching the electric charges of the floating gates of the memory elements to reach a desired threshold voltage.
REFERENCES:
patent: 5467309 (1995-11-01), Tanaka et al.
patent: 5682346 (1997-10-01), Yamamura et al.
patent: 5784316 (1998-07-01), Hirata
patent: 5959882 (1999-09-01), Yoshida et al.
patent: 3-130995 (1991-06-01), None
patent: 9-55092 (1997-02-01), None
Hitachi , Ltd.
Lam David
Miles & Stockbridge P.C.
LandOfFree
Non-volatile memory and method of non-volatile memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile memory and method of non-volatile memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory and method of non-volatile memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2998108