Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-01-05
2002-12-03
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06489796
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with a potential generating circuit boosting an externally applied power supply potential.
2. Description of the Background Art
Conventionally, a dynamic random access memory (DRAM) is provided with a boost circuit generating a potential higher than an externally applied power supply potential for driving a word line of a memory array.
FIG. 16
is a diagram showing an arrangement of the memory cell of the DRAM.
Referring to
FIG. 16
, a memory cell MC includes: an N channel MOS transistor
302
connected between a bit line BL and a storage node SN and having its gate connected to a word line; a capacitor
304
having its one end connected to storage node SN and the other end connected to a cell plate potential Vcp.
A substrate of N channel MOS transistor
302
is in most cases set at a negative back gate potential Vbb when a P type substrate is used. Cell plate potential Vcp applied to the other end of the capacitor is in most cases set at a potential half power supply potential Vcc.
Here, assume that an H (High) level is written as data to memory cell MC. Then, power supply potential Vcc is applied to bit line BL and N channel MOS transistor
302
is rendered conductive upon activation of word line WL. Power supply potential Vcc is transmitted to storage node SN.
FIG. 17
is a diagram shown in conjunction with a potential applied to N channel MOS transistor
302
when data at the H level is written to the memory cell.
Referring to
FIG. 17
, assume that storage node is initially set at a ground potential and then attains to power supply potential Vcc by application of power supply potential Vcc from bit line BL. In this case, N channel MOS transistor
302
has its drain D, source S, and gate G respectively connected to a bit line; storage node SN, and word line. When storage node SN attains to power supply potential Vcc, a large voltage of Vbb−Vcc is applied as a substrate bias voltage Vbs of N channel MOS transistor
302
because of substrate potential Vbb.
Inherently, a threshold voltage Vth of an access transistor used for the memory cell is set at a value greater than a threshold voltage of an N channel MOS transistor used for a usual peripheral circuit to reduce a subthreshold leakage current and to enhance refresh properties. As stated previously, if the source potential and substrate bias voltage Vbs increase, the threshold voltage of N channel MOS transistor
302
increases due to a substrate bias effect.
FIG. 18
is a graph showing a relationship between substrate bias voltage Vbs and threshold voltage Vth.
Referring to
FIGS. 17 and 18
, assume that the threshold voltage is Vt
0
when substrate bias voltage Vbsr of N channel MOS transistor
302
is 0V.
When an L level is written to;storage node SN of the memory cell and the potential at storage node SN is 0V, the value of substrate bias voltage Vbs equals to substrate potential Vbb and threshold voltage Vth equals to threshold voltage Vt
1
shown in FIG.
18
.
Then, when data at the H level is written to the memory cell, storage node SN attains to potential Vcc, so that substrate bias voltage Vbs equals to |Vbb−Vcc|. Thus, threshold voltage Vth increases to attain to threshold voltage Vt
2
shown in FIG.
18
.
To enable transmission of power supply potential Vcc at the H level of bit line BL to storage node SN without causing any voltage drop, the potential of word line WL must be set; at a value higher than power supply potential Vcc by threshold voltage Vth.
FIG. 19
is a graph showing a relationship between a voltage written to the memory cell and a potential for activating the word line required therefor.
Referring to
FIG. 19
, a line G
1
represents a potential transmitted to storage node SN of the memory cell. A line G
2
represents a value obtained by adding the threshold voltage of the memory cell transistor to the potential of line G
1
. When 0V at the L level is written to the memory cell, the difference between lines G
1
and G
2
corresponds to threshold voltage Vt
1
shown in FIG.
18
. On the other hand, when power supply potential Vcc at the H level is to be written to the memory cell, line G
2
becomes higher than line G
1
by threshold voltage Vt
2
. A lower limit of the activation potential actually applied to the word line is obtained by further adding a margin to the potential of line G
2
as depicted by a line G
3
.
The actual activation potential of the word line is set with reference to the case where the writing voltage requiring a high activation potential is power supply potential Vcc. Thus, line G
3
equals to that indicating the activation potential of word line WL when power supply potential Vcc is changed.
Namely, the potential required for activation of the word line changes in accordance with the change in power supply potential Vcc and in consideration of the change in the substrate bias effect of the threshold voltage.
The activation potential of word line WL is in most cases boosted potential Vpp obtained by internal boosting.
FIG. 20
is a diagram shown in conjunction with a basic principle of a conventional boost circuit generating boosted potential Vpp.
Referring to
FIG. 20
, a boost circuit
310
includes: a diode
312
having its anode and cathode respectively connected to power supply potential Vcc and a node N
11
for precharging node N
11
to power supply potential Vcc; an oscillation circuit
316
generating a clock signal for a boosting operation; a capacitor
314
having its one end and the other end respectively connected to node N
11
and an output of clock generation circuit
316
; and a diode
318
having it anode connected to node N
11
and cathode outputting boosted potential Vpp. When node N
11
is precharged to power supply potential Vcc by diode
312
for precharging, node N
11
is boosted to a value twice power supply potential Vcc from power supply potential Vcc by a clock signal generated by oscillation circuit
316
of which L and H levels respectively correspond to a ground potential and power supply potential Vcc. The boosted potential is output as boosted potential Vpp through diode
318
.
It is noted that the foregoing description ignores a voltage drop in a forward direction due to diodes
312
and
318
for simplification.
FIG. 21
is a circuit diagram showing an actual arrangement of a boost circuit.
Referring to
FIG. 21
, a boost circuit
320
includes capacitors
321
and
322
having their one ends receiving clock signals CLK. The other end of capacitor
321
is connected to a node N
12
. The other end of capacitor
322
is connected to a node N
13
.
Boost circuit
320
further includes: an N channel MOS transistor
324
diode-connected to N
12
from a node to which power supply potential Vcc is applied; an N channel MOS transistor
326
diode-connected to N
13
from the node to which power supply potential Vcc is applied; and an N channel MOS transistor
328
connected between nodes N
12
and N
14
and having its gate connected to node N
13
and its back gate supplied with substrate potential Vbb. Boosted potential Vpp is output from node N
14
.
Before operation, nodes N
12
and N
13
are precharged to power supply potential Vcc or a potential lower than power supply potential Vcc by a threshold voltage of the N channel MOS transistor. The precharge is performed by N channel MOS transistors
324
and
326
which are diode-connected.
Clock signal CLK is input, and the potential at one ends of capacitors
321
and
322
are boosted to power supply potential Vcc from 0V.
Then, nodes N
12
and N
13
attain to a potential twice power supply potential Vcc from power supply potential Vcc due to capacitive coupling. The potential twice power supply potential Vcc at node N
12
is supplied to node N
14
through N channel MOS transistor
328
. At the time, boosted potential Vpp decreases by threshold voltage Vthn of N channel MOS transistor
328
.
Namely, in the circuit shown in
FIG. 21
, the high potential at
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Vinh P.
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