Electricity: power supply or regulation systems – Output level responsive – Using an impedance as the final control device
Reexamination Certificate
2000-11-20
2002-12-03
Berhane, Adolf Deneke (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using an impedance as the final control device
C327S540000
Reexamination Certificate
active
06489759
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention lies in the electronics field and in the semiconductor technology field. More specifically, the invention relates to voltage supply for an electronic circuit which supplies the electronic circuit during a standby mode with at least two supply voltages (VDD
1
, VDD
2
, . . . ) having different levels. Each of the supply voltages of the electronic circuit is supplied in the active operating mode via a respective active-voltage controller that is allocated to each level, respectively.
Many electronic circuits, for instance eDRAMs (embedded DRAMs), have two operating modes, namely a standby mode and an active mode. In the standby mode, the circuit is supplied with stable voltages such that the information stored therein is maintained. In the standby mode, the sum of the currents that are consumed by the circuit should be as small as possible.
By contrast, in the active mode, in which the electronic circuit is working and performing data processing operations, the sum of the currents supplied to the circuit is relatively large, while the voltages remain substantially the same.
It is well known that an eDRAM, as an example of such an electronic circuit, must be supplied with different voltage levels both in the standby mode and in the active mode; for instance, an amplified word line voltage with a voltage value of approx. 3.5 V (+/−10%) for a read/write operation, local and global supply voltages VBLH with voltage values of 1.8 V (+/−10%) for read amplifiers (S/A), a bias voltage VPL with total voltage values of VBLH/
2
(i.e. 0.9 V) for reducing loads that are generated across the eDRAM cell by the electric field, a bit line equalization voltage VBLEQ with voltage values of VBLH/
2
(i.e. approx. 0.9 V) which is applied prior to a read operation, and an eDRAM substrate bias voltage VBB with voltage values of approx. −1 V for minimizing leakage currents and increasing the cell retention time. Depending on the type of eDRAM used, all these voltages are used, or only some of them, or additional voltages as well. In addition, there are even voltages over the voltage that is externally fed to the semiconductor chip in which the eDRAM is embedded, for which voltage pumps are needed, for instance in order to generate a voltage of 3.8 V from an externally applied voltage of 3.3 V.
In existing configurations, in order to satisfy the requirement of a low power consumption, separate controllers are used to generate the individual voltages in the active and standby modes. An example of this is illustrated in
FIG. 3
in a schematic block diagram.
An eDRAM
2
is embedded in a silicon semiconductor chip. The eDRAM
2
is supplied with voltages by controller units
4
,
5
,
6
,
7
,
8
, and it is connected to a logic unit
3
. The controller units
4
to
8
are supplied via pads
9
,
10
(contact terminals) with an external supply voltage CE (via the pad
9
) by a voltage source
11
that delivers a voltage of approx. 3.3 V. A reference potential T is connected via the pad
10
. Additional pads
18
serve for the input/output of additional signals. From the external voltages, the controller units
4
to
8
generate the desired supply voltages with values of 2.5 V (controller unit
4
), 0.9 V (controller unit
5
), 0.9 V (controller unit
6
), 1.8 V (controller unit
7
), and 3.8 V (controller unit, i.e., pump
8
). In order to be able to deliver the voltage with 3.8 V, the controller unit
8
must be realized as a voltage pump.
The construction of the controller units
4
,
5
is represented, by way of example in FIG.
4
: each of the controller units
4
and
5
comprises an active controller
12
and a standby controller
13
, which are charged with the external high voltage CE and the external low voltage T as represented in the figure. In the active mode the controller
12
works with a relatively large current I
1
, while in the standby mode the controller
13
delivers the respective desired voltages VDD
1
and VDD
2
with a relatively low current I
0
(I
1
>>I
0
). The voltages VDD
1
and VDD
2
have values of 2.5 V and 0.9 V, respectively, as represented in FIG.
3
. The voltage VDD
1
is therein generated from the external voltage CE, while the voltage VDD
2
is generated from the low voltage T. Lastly,
FIG. 5
shows the construction of such a controller
13
consisting of N and P channel MOS transistors, resistors, and a reference voltage source. This controller construction is of a conventional type and therefore requires no further explanation.
It is already clearly evident from
FIGS. 3 and 4
that the outlay for the individual controller units
4
to
8
is substantial, since each controller unit comprises two controllers
12
and
13
, which must be readied for active and standby modes. This requires a relatively large area on the semiconductor chip
1
.
It must also be taken into account that the controllers for the standby mode, in particular, require an extremely precise design, since the current flowing in standby mode is largely determined by the closed-circuit current of the controller.
SUMMARY OF THE INVENTION
The object of the invention is to provide a voltage supply for an electronic circuit requiring at least two supply voltages with different levels, which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which is of simple construction, occupies an optimally small area on a semiconductor chip, and has a very low natural-current consumption.
With the above and other objects in view there is provided, in accordance with the invention, a voltage supply configuration for an electronic circuit having an active mode and a standby mode, and requiring at least two supply voltages with mutually different levels. The supply voltages are supplied to the electronic circuit in the active operating mode via respective active-controllers each allocated a respective voltage level. There is further provided a standby voltage controller for a highest supply voltage; and a voltage divider connected in series with the standby voltage controller and configured to generate, during the standby mode of the electronic circuit, when the active-voltage controllers are switched off, the supply voltages from the highest supply voltage.
In accordance with an added feature of the invention, the voltage divider comprises a plurality of taps connected via switches to the active-voltage controllers, and the active-voltage controllers are configured to be switched off by a standby signal.
In accordance with an additional feature of the invention, the voltage divider is connected between two transistors two transistors, the control electrodes of which are controlled via a standby signal and a phase-shifted standby signal.
In accordance with another feature of the invention, the highest supply voltage is a word line voltage of the electronic circuit.
In accordance with a further feature of the invention, the standby voltage controller contains a pump circuit. In a preferred embodiment, the voltage divider is formed with a plurality of transistors.
By way of example, the electronic circuit is a DRAM embedded in a semiconductor body.
In other words, the configuration for supplying voltages during a standby mode to an electronic circuit having at least two supply voltages with different levels, in which the supply voltages of the electronic circuit are supplied in an active operating mode thereof via respective active-controllers respectively allocated to each voltage level, comprising a voltage splitter connected in series with a standby voltage controller for a highest supply voltage, wherein, during the standby mode when the active-voltage controllers are switched off, the voltage splitter generates the supply voltages from the highest supply voltage.
The taps of the voltage divider are connected via switches to the active-voltage controllers for the remaining supply voltages, which controllers can be switched off using a standby s
Acharya Pramod
Täuber Andreas
Berhane Adolf Deneke
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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