Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Including memory
Reexamination Certificate
2000-06-30
2002-10-29
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Including memory
C377S028000, C377S034000
Reexamination Certificate
active
06473484
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to digital counters, and more specifically, to a digital counter using a sequence of bit combinations chosen to distribute storage cell changes uniformly, which equalizes fatigue among the storage cells in the counter. This invention also relates to general purpose computers using non-volatile storage to store count values.
DESCRIPTION OF THE PRIOR ART
Binary codes have been adapted for different purposes in the history of the art. The BCD (Binary Coded Decimal) and Gray codes circuits. The BCD code, which is well known in the art, was created to facilitate the translation of standard binary data to human interface compatible decimal information. The Gray code, which is also well known in the art, was created to minimize the bit changes between codes, allowing only one bit change per count step in a counting sequence. This minimizes the impact of a single bit error in counters and communication systems and can reduce power consumption in some circuits. With certain types of non-volatile storage, fatigue due to state changes in binary cells creates a limited lifetime. FLASH and EEPROM (Electrically Erasable Programmable Read-Only Memory) exhibit lifetimes which may range as low as ten thousand state changes before the storage cell fails. Counters and other digital circuits which utilize non-volatile storage elements are of limited life span. This type of storage for counters can be used in RTC (Real Time Clock) circuits in personal computers and other systems such as event counters which have slowly changing count values and must maintain integrity during power failure or power down states.
Therefore, a need exists to reduce the impact of cell change fatigue in circuits employing these forms of non-volatile storage. The standard binary code does not fill this need, since the least significant bit of a standard binary counter changes with every clock, while the most significant bit only changes twice before the counter overflows. The Gray code also does not fill this need, since the code was designed to minimize changes in the number of bit per count cycle and not to spread the number of changes between all of the cells in the counter or other digital circuit.
The present invention fills this need by using a type of binary coding which subjects each cell in the counter or other digital circuit to the same number of changes for a complete count cycle. When this type of code is a Gray code it is known in the mathematical arts as a “Uniformly Balanced Gray Code”. This maximizes the reliability of the counter or other digital circuit.
The limitation that this code be a Gray code is not necessary to the present invention, but is preferred for more reliable operation of the counter, since only one bit changes state per count. Another type of code known as “Balanced Gray Code” could be used, but is not preferred because it makes the number of transitions on each bit cell per counter cycle only approximately equal. This would enhance, but not maximize the reliability of the counter.
While the primary purpose of the invention is to increase the reliability of storage cells used to hold a count value, other applications for this counter and method for counting are envisioned, which include encoding and decoding secure transmissions.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, it is an object of the present invention to provide a digital counter and a method for counting to increase the life span of storage cells.
In accordance with another embodiment of the present invention, it is an object of the present invention to provide a method for counting within a microprocessor or microcontroller based system which increases the life span of storage cells used to maintain count values.
In accordance with another embodiment of the present invention, it is an object of the present invention to provide a method for counting within software executing on a digital computer which increases the life span of storage cells used to maintain count values.
In accordance with another embodiment of the present invention, it is an object of the present invention to provide a counter and method for counting which enhance the performance of a counting system such as providing security by using a counting sequence as part of an encoding or decoding process.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENT
In accordance with one embodiment of the present invention, a digital counter is implemented. This counter uses a state logic which creates a uniform distribution of state changes among the bits in the counter. Creating a uniform distribution of state changes increases the reliability of the counter by distributing fatigue evenly among the individual cells in the storage for the count value, and may be used for other performance advantages including increased security.
In accordance with another embodiment of the present invention, a method for counting is provided for a microprocessor or microcontroller based system using non-volatile storage either integrated or provided externally. This method will increase the reliability of the storage, since the individual cells will be fatigued at the same rate, and may provide other performance advantages to a microprocessor system such as increased security.
In accordance with another embodiment of the present invention, a method for counting is provided for use in a general purpose digital computer using non-volatile storage. This will increase the reliability of the storage, since the individual cells will be fatigued at the same rate, and may provide other performance advantages to a digital computer such as increased security.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5450460 (1995-09-01), Stodieck
patent: 5675622 (1997-10-01), Hewitt et al.
patent: 0484259 (1991-10-01), None
patent: 2707027 (1993-06-01), None
Baker & Botts L.L.P.
Microchip Technology Incorporated
Wambach Margaret R.
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