Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
1998-08-26
2002-12-24
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S401000, C438S004000, C438S014000, C438S015000
Reexamination Certificate
active
06498361
ABSTRACT:
FIELD OF INVENTION
The present invention relates to configurable integrated circuits, such as ASICs and gate arrays, and particularly, the invention relates to electronic identification of configurable integrated circuit designs.
BACKGROUND
Configurable integrated circuits are integrated circuits (ICs) that are customized and fabricated to meet the specific needs of a particular user, typically an IC designer. Configurable ICs include application-specific integrated circuits (ASICs), such as gate arrays which are partially customizable, and standard cells which are completely customizable by a user of such circuits.
In particular, gate arrays are popular among IC designers as a generally economical way of creating unique ICs for use in their electronic designs. Gate arrays are generally composed of a predefined matrix (or array) of function blocks, which can be formed into a specific, unique circuit by interconnecting the function blocks. Because gate arrays are already predesigned and often prefabricated up to the point where a user can customize them, gate arrays are often used as low-cost prototypes in the electronics design process.
The fabrication of configurable ICs is usually done on a silicon wafer. The wafer is divided into multiple die, where each die is eventually separated from the rest of the wafer to become an individual IC. Once the die have been separated, the die are tested and packaged.
Typically a single IC design is placed on a wafer. In other words, the same design is placed in each die on the wafer. Placing different IC designs into the distinct die on the wafer is generally undesirable because the die are not always easily visually distinguishable. IC designs become easily confused and mixed together during the testing and packaging process.
Frequently, an IC designer using a configurable IC will only require very few configurable ICs to be manufactured and customized for their use, especially when the IC is to be a prototype. It is not unheard of that IC designers require only one prototype to be manufactured. IC designers often do not need (or want to pay for) the multiple ICs that are formed as a result of placing the designer's design into each die on the wafer.
If the IC designer desires only one custom IC, however, as a prototype or for another low volume production reason, the manufacturer is faced with two choices: (1) either place only one design on a wafer, or (2) place multiple distinct designs on a single wafer. The first option, placing only one design on a wafer, is expensive and wasteful for the manufacturer. Further, if the configurable IC is sold based on charging the IC designer low fees for prototypes, it becomes strongly desirable to place multiple designs on a wafer so that the cost of producing the prototypes for the new design may be shared with other designs.
Still, if the manufacturer cannot identify which design is included on which die, placing multiple designs on a wafer will become burdensome and drive costs upward. Accurate testing and packaging may not occur or the IC designer may not receive the correct design. Hence, most manufacturers that are involved in low volume production of particular designs try to avoid placing multiple designs on a single wafer.
SUMMARY OF THE INVENTION
To minimize the burdens of fabricating multiple distinct IC designs on a single wafer, a small memory is included in each die region. In one embodiment, the memory is a mask-programmed ROM. The memory stores information specific to the design included in the particular die region. For instance, the. memory may include a circuit design identifier in one embodiment. In another embodiment, the memory may include a customer identifier. Once the fabrication process is complete and the die separated from the wafer, the memory can be electronically read to identify the circuit design included. In this manner, design misidentification is minimized. The design identifier can further be used to select test patterns for use in testing the IC.
In still other embodiments of the invention, proprietary technology identifiers are stored in the memory. These proprietary technology identifiers are useful for identifying any proprietary technology that may be incorporated in the circuit design. Such information is particularly useful to owners/licensors of the proprietary technology in tracking where and by whom the proprietary technology is being utilized.
REFERENCES:
patent: 4446475 (1984-05-01), Gercekci et al.
patent: 5408131 (1995-04-01), Khatri et al.
patent: 5452297 (1995-09-01), Hiller et al.
patent: 5732207 (1998-03-01), Allen et al.
patent: 5787174 (1998-07-01), Tuttle
patent: 5894422 (1999-04-01), Chasek
patent: 0360164 (1990-03-01), None
Fliesler Dubb Meyer & Lovejoy LLP
Lightspeed Semiconductor Corporation
Meier Stephen D.
LandOfFree
Design information memory for configurable integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Design information memory for configurable integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design information memory for configurable integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2995526