Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2000-02-22

2002-12-03

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S538000, C327S543000

Reexamination Certificate

active

06489833

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit, and, more particularly, a semiconductor integrated circuit device suitable for high-speed operation.
BACKGROUND ART
In an integrated circuit using CMOS transistors, characteristics fluctuation exists due to variations in transistor dimension caused by a fabrication process and a change in the environment, such as temperature or supply voltage, during operation.
As described in “1994 symposium on VLSI technology digest of technical papers” (June, 1994), pp. 13 to 14, as an MOS transistor becomes finer, fluctuation in basic parameters, such as a threshold value due to the characteristics fluctuation caused by a fabrication process, becomes larger.
FIG. 12
schematically shows delay of a CMOS circuit with respect to the device feature size of a MOS transistor and the range of variation. In designing a CMOS integrated circuit, the worst delay in
FIG. 12
has to be considered. By an increase in the range of variation, even if the device becomes finer, high-speed operation is limited by the worst delay. If the delay of the CMOS circuit can be made “typical” or “best” by suppressing the characteristics fluctuation, the high processing speed of the circuit can be promoted.
As a method of suppressing the characteristics fluctuation by improving the circuit, in Nikkei Electronics 7-28 (1997), pp. 113 to 126, a technique is described as follows: A leakage current of a monitor is measured and a substrate bias is changed so that the current becomes a constant value. Delay of a replica is also measured. A change in delay is detected, and the supply voltage is changed, thereby suppressing the characteristics fluctuation.
According to the technique described in Nikkei Electronics 7-28 (1997), pp. 113 to 126, the substrate bias is controlled so that the leakage current of the MOS transistor when the gate voltage is 0V becomes a constant value. Since the leakage current of the MOS transistor increases as the temperature rises, the threshold has to be increased by applying the substrate bias. In this case, there is a drawback such that the ON current of the MOS transistor conspicuously decreases by deterioration in mobility and increase in the threshold due to the temperature rise, and as a result, the processing speed of the circuit decreases. A filter having an inductance and a capacitance is formed outside of the chip and used to generate a supply voltage for delay control. Since it takes a few &mgr; seconds until an output voltage of the filter is stabilized, stabilization time of a control signal is long, and the signal tends to be unstable. Consequently, control accuracy cannot be raised. When the capacitance and the inductance used for the filter are formed on the same chip on which a circuit to be controlled is also mounted, the fact that they occupy a large area becomes a problem.
Japanese Unexamined Patent Application No. 4-247653 discloses a concept such that a delay detector is provided to suppress delay variations of a gate circuit and the substrate bias of the gate circuit is controlled on the basis of the detection result.
Japanese Unexamined Patent Application No. 5-152935 also discloses a concept such that the substrate bias is controlled by using a capacitive filter and a charge pump to suppress device variations, thereby improving the yield.
Further, Japanese Unexamined Patent Application No. 8-274620 discloses a concept such that the delay amount of a circuit is detected by using a reference clock signal and the substrate bias of the circuit is controlled on the basis of the detection result.
DISCLOSURE OF INVENTION
It is an object of the invention to solve the problems of the conventional techniques.
More specifically, the inventors of the present invention have examined the problems in detail, which may occur when the conventional techniques are applied to a real semiconductor integrated circuit device, and propose the present invention. The present invention is to provide a semiconductor integrated circuit constructed by an MOS (MIS) transistor, in which characteristics fluctuation of a CMOS circuit is suppressed in short stabilization time and in a small area to thereby raise the control accuracy and improve the operating speed of the main circuit.
In order to achieve the subject, a semiconductor integrated circuit device as a representative embodiment of the invention includes a logic circuit for performing a predetermined process and a substrate-bias controller for supplying a substrate bias to an MIS transistor constructing the logic circuit. The logic circuit takes the form of an MIS transistor, and the substrate-bias controller supplies a suitable substrate bias to the MIS transistor in accordance with the characteristics fluctuation of the logic circuit. The threshold of the MIS transistor is changed by changing the substrate bias and the characteristics fluctuation of the logic circuit is suppressed. The characteristic of the logic circuit is detected as a delay, and the amount of change of the delay is converted into a digital amount. As a result, the substrate-bias controller can be constructed by a digital circuit, so that the stabilization time of the control voltage is shortened and the circuit scale is reduced.
A typical construction example of the invention is a semiconductor integrated circuit device including: a logic circuit for performing a predetermined process; a digital-to-analog converter for generating a substrate bias for controlling a threshold of an MIS transistor constructing the logic circuit; a voltage-controlled circuit for outputting a control signal in accordance with a delay signal; and a delay detector which can vary operating speed, characterized in that the delay detector receives a clock signal supplied from the outside and outputs a delay signal. The voltage-controlled circuit receives the delay signal of the delay detector and outputs a control signal according to delay time. The digital-to-analog converter receives the control signal supplied from the voltage-controlled circuit and generates a voltage according to the control signal, and the operating speed of the logic circuit and the delay detector is controlled by voltage supplied from the digital-to-analog converter.
In the example, since the main part of the controller deals with a digital signal, the circuit configuration is simple. The controller part and the circuit to be controlled can also be formed on different chips.
As a typical example of the circuits, the delay detector is comprised of a clock-duty modulator and a delay monitoring circuit. The voltage-controlled circuit is constructed by a delay comparator, the digital-to-analog converter is constructed by a substrate-bias generator, and the clock-duty modulator receives the clock signal from the outside and outputs a clock signal of an arbitrary clock duty ratio.
As another example, the delay monitoring circuit outputs an output signal of the clock-duty modulator with a predetermined delay. The delay comparator obtains a delay difference between the output signal of the clock-duty modulator and the output signal of the delay monitoring circuit by comparison, and outputs a signal according to the difference. The substrate-bias generator generates a substrate bias according to the output signal of the delay comparator, and the delay in both the logic circuit and the delay monitoring circuit is controlled by the substrate bias generated by the substrate-bias generator.
As another typical example, the delay detector is comprised of a divider and an oscillator, the voltage-controlled circuit is comprised of a phase-frequency detector and a phase-frequency controller, and the digital-to-analog converter is constructed by a voltage generator. The clock signal from the outside is supplied to the divider by which the frequency of the clock signal is optionally divided, the phase-frequency detector compares a phase and a frequency of a frequency-division signal of the divider with those of an output signal of the oscillator and produces an o

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