Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1999-10-25
2002-10-01
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S528000, C257S266000
Reexamination Certificate
active
06459108
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor configuration suitable for passively limiting an electric current, and to an implementation of the novel configuration.
To supply an electrical consumer (load device) with an electric current, the consumer is connected to a line branch of an electrical supply network via a switching device. To protect the consumer against excessive currents, particularly in the event of a short circuit, low-voltage technology uses a switching device with an isolator, for which a fuse is generally used, protecting the line branch and with a mechanical power switch having a switching time of markedly more than one millisecond (1 ms). If a plurality of consumers are operated at the same time in a line branch and a short circuit occurs in only one of these consumers, then it is greatly advantageous if the consumers not affected by the short circuit can continue to operate without fault and only the consumer affected by the short circuit is switched off. To this end, current-limiting components (limiters) connected immediately upstream of each consumer are required. Each of the current limiters reliably limit the current of the prospective short-circuit current to a predetermined, noncritical overcurrent value within a time of markedly less than 1 ms, and hence before the isolator provided for the line branch is triggered. In addition, these current-limiting components should work passively without any driving and should be able to tolerate voltages of, typically, up to 700 V and from time to time up to 1200 V which are present during current limiting. Since the power loss which then occurs in the component is very high, it would be particularly advantageous if the passive current limiter were also to reduce the current to values markedly below the predetermined overcurrent value automatically, with additional voltage uptake (intrinsically safe component).
The only commercially available passive current limiter known to the inventors is a device described by T. Hansson in a paper titled “Polyethylen-Stromwächter für den Kurzschlu&bgr;schutz” [Polyethylene current monitor for short-circuit protection], ABB Technik 4/92, pages 35-38. That device is distributed under the product name PROLIM and is based on current-dependent conductivity of the grain boundaries of the material used in the device. When the device is used relatively frequently for current limiting, however, the current saturation value at which the current is limited may be changed.
Otherwise, only active current limiters are used in general, which detect the current and limit it by active control if a predetermined maximum current value is exceeded. Such a semiconductor-based active current limiter is described in German published patent application DE 43 30 459. That device has a first semiconductor region of a predetermined conductivity type which is allocated a respective electrode on mutually remote surfaces. In the first semiconductor region, further semiconductor regions of the opposite conductivity type are formed at a distance from one another between the two electrodes. Channel regions of the first semiconductor region are formed between each of the further semiconductor regions and are oriented perpendicularly to the two surfaces of the first semiconductor region (vertical channels). A vertical flow of current between the two electrodes is routed through these channel regions and limited thereby. To control the flow of current between the two electrodes, a gate voltage is applied to the oppositely doped semiconductor regions in the first semiconductor region. The gate voltage controls the resistors in the channel regions.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor configuration, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which can be used for passively limiting electric currents when a critical current value is exceeded. It is a further object of the invention to provide a current limiter device with such a semiconductor configuration.
With the foregoing and other objects in view there is provided, in accordance with the invention, an claim 1.
A semiconductor configuration, comprising:
a first electrode and a second electrode;
a first semiconductor region having a first surface formed with at least one contact region in contact with the first electrode, having a second surface in contact with the second electrode, and defining a current path between the first and second electrodes;
a second semiconductor region disposed to form a p-n junction with the first semiconductor region and an associated depletion zone;
a third semiconductor region disposed to form a p-n junction with the first semiconductor region and an associated depletion zone;
the third semiconductor region having a surface not adjoining the first semiconductor region an being insulated for charge storage charges in the third semiconductor region;
the first semiconductor region being formed with at least one channel region in the current path between the first and second electrodes and, upon attaining a predetermined saturation current between the first and second electrodes, the depletion zones of the p-n junctions pinching off the channel region and limiting the current to a value below the saturation current.
In other words, the novel semiconductor configuration is formed with:
a) a first semiconductor region, which, on a first surface, is in contact with a first electrode in at least one contact region, and is in contact with a second electrode on a second surface;
b) at least one second semiconductor region, which forms a p-n junction with the first semiconductor region;
c) at least one third semiconductor region, which forms a p-n junction with the first semiconductor region;
where
d) the third semiconductor region is insulated on its surface not adjoining the first semiconductor region, so that electrical charges can be stored in the third semiconductor region; and
e) the first semiconductor region has at least one channel region which is situated in a current path between the two electrodes and, when a predetermined saturation current is reached between the two electrodes, is pinched off by depletion zones of said p-n junctions, after which the current is limited to a value below the saturation current.
This semiconductor configuration uses an advantageous combination of physical effects in the channel region to limit a current, particularly a short-circuit current, to an acceptable current value automatically and without active driving. In addition, the semiconductor configuration can, in principle, maintain this acceptable current value, on account of the charge storage in the electrically insulated third semiconductor region and the resultant continuous pinch-off of the channel region, even with subsequent voltage reductions at the two electrodes.
In accordance with an added feature of the invention, the second semiconductor region is formed inside the first semiconductor region below the contact region and projects beyond the contact region in all directions parallel to the surface of the first semiconductor region. This embodiment reaches particularly high breakdown strength.
The third semiconductor region preferably surrounds the contact region parallel to the first surface of the first semiconductor region.
In accordance with an additional feature of the invention, the second surface of the first semiconductor region is remote from and facing away from the first surface. This feature results in a vertical and thus particularly surge-proof design.
In accordance with another feature of the invention, the at least one contact region is one of a plurality of contact regions on the first surface. In other words, the first surface is preferably provided with a plurality of contact regions which, in particular, are allocated a common electrode.
In acco
Bartsch Wolfgang
Mitlehner Heinz
Stephani Dietrich
Greenberg Laurence A.
Locher Ralph E.
Loke Steven
Nadav Ori
Siemens Aktiengesellschaft
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