Semiconductor integrated circuit and testing method thereof

Details Semiconductor integrated circuit and testing method thereof Semiconductor integrated circuit and testing method thereof

2001-09-06

2002-11-05

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

06476633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor integrated circuit made up by integrating a plurality of N channel MOSFETs with a plurality of P channel MOSFETs, and more particularly, to a semiconductor integrated circuit comprising the plurality of the respective channel MOSFETs, each incorporating at least a MOSFET having a different threshold voltage, and also to a testing method thereof.
2. Description of the Related Art
Portable information equipment, typically such as PHS (personal handy-phone system) and PDA (portable data assistant), have recently come into widespread use. A semiconductor integrated circuit (referred to hereinafter as IC) is in use as one of the components of the portable information equipment. There has been a strong demand that the IC can achieve reduction in power consumption without degrading its performance in respect of processing speed.
An IC using the CMOS technology is known for its lower consumption of power in comparison with an IC using the bipolar technology or the EDMOS technology.
However, even with the IC using the CMOS technology, the magnitude of power consumption thereof has come to pose a problem as a result of shift of operation frequencies of ICs to higher frequencies taking place lately.
The power consumption P of a CMOS logic gate circuit in the IC using the CMOS technology is generally approximated by the following expression:
P∝K·C·Vdd
2
·f+I leak·Vdd  (1)
where K=switching probability,
C=output load capacity of the CMOS logic gate circuit, Vdd=power source voltage,
f=operation frequency, and
I leak=subthreshold leak current.
The subthreshold leak current will be further described hereinafter. A symbol “·” in expression (1) denotes multiplication, and the same applies to other expressions referred to later.
When the IC is in an operating mode (for example, when the CMOS logic gate circuit is in an operating state upon supply of a clock signal of a given frequency thereto), a first term of the expression (1) becomes dominant, and power consumption thereof will be proportional to the square of the power source voltage Vdd. On the other hand, when the IC is in a standby mode (when the operation of the CMOS logic gate circuit is in a suspended state upon supply of a clock signal thereto being inhibited), a second term of the expression (1) becomes dominant since the operation frequency turns to zero. As is evident from the expression (1), by lowering the power source voltage Vdd, the power consumption, particularly when the IC is in an operating mode, can be significantly reduced. Accordingly, there has been an increasing demand for ICs used in portable information equipment that can be operated at lower power source voltages.
As described in the foregoing, the power consumption of the IC can be reduced by lowering the power source voltage Vdd. However, the power source voltage Vdd at a reduced level results in an increase of gate propagation delay time tpd of the CMOS logic gate circuit making up the IC. The gate propagation delay time tpd of the CMOS logic gate circuits is generally approximated by the following expression:
tpd=C·Vdd/(Vdd−Vt)
&agr;
  (2)
where C=output load capacity of the CMOS logic gate circuit,
Vdd=power source voltage,
Vt=threshold voltage of switching MOSFETs, and
&agr;=factor determined, depending on the generation of a device 1≦&agr;≦2.
As is evident from the expression (2), the power source voltage Vdd at a reduced level results in a gradual increase of the gate propagation delay time tpd. It is further shown that if the power source voltage Vdd is lowered close to the threshold voltage Vt of a MOSFET, a denominator on the right side of the expression (2) becomes small in value, resulting in a significant increase in the gate propagation delay time tpd. It follows therefore that the threshold voltage Vt of the MOSFET needs to be lowered according as the power source voltage Vdd is lowered in order that the power source voltage Vdd is lowered without causing an increase in the gate propagation delay time tpd.
Meanwhile, as indicated by the second term of the expression (1), the power consumption (referred to hereinafter as standby power consumption) of the CMOS logic gate circuits when the IC is in a standby mode is substantially determined by leak current I
leak
. (referred to generally as subthreshold leak current) occurring when a voltage between the gate and the source of the MOSFET is at 0V. The subthreshold leak current I
leak
is generally approximated by the following expression:
I
leak
∝e x p{−Vt (S/In 10)}  (3)
where Vt=the threshold voltage of a MOSFET, and
S=subthreshold factor, one of numerical values indicating the characteristics of a MOSFET, and more specifically, a numerical value indicating the current—voltage characteristic in a region where a voltage between the gate and the source of the MOSFET is not higher than the threshold voltage Vt. With MOSFETs of the submicron order, the numerical value is generally on the order of 80 to 90 mV/decade.
As is evident from the expression (3), it is shown that if the threshold voltage Vt is set at low levels, the subthreshold leak current I
leak
will increase exponentially. For example, if the threshold voltage of a MOSFET making up an IC comprising a CMOS logic gate circuit is lowered by 0.3V, this will result in an increase of the subthreshold leak current I
leak
occurring when the IC is in a standby mode by three or four orders of magnitude.
As described in the foregoing, there is a trade-off relationship between the subthreshold leak current I
leak
when the threshold voltage Vt is changed and the gate propagation delay time tpd. With ICs comprising a CMOS logic gate circuit, the threshold voltage Vt is generally set such that the gate propagation delay time tpd as required can be achieved while meeting the standby power consumption as allowed in product specification and so forth. It has become extremely difficult, however, to reconcile the subthreshold leak current I
leak
which is satisfactory with the gate propagation delay time tpd which is also satisfactory in the face of the recent demand for lowering the power source voltage Vdd.
In connection with the CMOS technology, there has been disclosed in the following literature a technology whereby the standby power consumption can be reduced without sacrificing operation speed characteristic (for example, the gate propagation delay time tpd); the title of the literature: “1-V Power Supply High—Speed Digital Circuit Technology with Multithreshold —Voltage CMOS”.IEEE Journal of Solid-State Circuits 30[8], pp. 847-854, 1995.
The technology disclosed in the literature described above is called a Multi—Threshold Voltage CMOS (referred to hereinafter as MT CMOS) technology. The MT CMOS technology disclosed in the literature described above will be briefly described hereinafter.
In an IC using the MT CMOS technology, a power source voltage is supplied to the logic gate circuit thereof via a pseudo power source voltage line on the high potential side and a pseudo power source voltage line on the low potential side.
The logic gate circuit comprises P channel MOSFETs and N channel MOS FETs, both having low threshold voltages. A power source voltage on the high potential side is supplied to the pseudo power source voltage line on the high potential side via a switch made up of a P channel MOSFET having a threshold voltage higher than that of the P channel MOSFETs making up the logic gate circuit. A power source voltage on the low potential side is supplied to the pseudo power source voltage line on the low potential side via a switch made up of a N channel MOSFET having a threshold voltage higher than that of the N channel MOSFETs making up the logic gate circuit.
When the N channel MOSFETs making up the IC and the switch made up of the N channel MOSFET are looked at as four-terminal devi

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