Semiconductor integrated circuit device including logic gate...

Details Semiconductor integrated circuit device including logic gate... Semiconductor integrated circuit device including logic gate...

2001-03-26

2002-11-19

Christianson, Keith (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C326S033000

Reexamination Certificate

active

06483165

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly to a configuration for achieving reduction of current consumption as well as high-speed operation of a semiconductor integrated circuit device including a logic gate constituted of a CMOS transistor.
2. Description of the Background Art
In the field of semiconductors, enhancement of integration and reduction of supply voltage are being promoted nowadays.
Since MOS transistors constituting an internal circuit have threshold voltage, the threshold voltage should be made smaller in order to secure a high-speed operation. However, a problem of a dramatic increase in the leakage current arises if the threshold voltage is decreased.
One scheme for solving this problem is a hierarchical power supply system. The hierarchical power supply system employed in a conventional semiconductor integrated circuit device will be described using FIG.
67
.
In
FIG. 67
, a plurality of stages of CMOS inverters X
1
, X
2
, X
3
. . . connected in cascade are shown as forming one example of an internal circuit.
CMOS inverters X
1
, X
2
and X
3
each include a PMOS transistor and an NMOS transistor. A main supply line L
1
, a sub-supply line L
2
, a main ground line L
3
and a sub-ground line L
4
for applying an operation supply voltage are arranged for inverters X
1
-X
3
.
A switching transistor T
1
is placed between main supply line L
1
and sub-supply line L
2
. Between main ground line L
3
and sub-ground line L
4
, a switching transistor T
2
is arranged.
Switching transistor T
1
is brought to a conducting state in response to a hierarchical power supply control signal/&phgr;c to electrically connect main supply line L
1
and sub-supply line L
2
.
Switching transistor T
2
is brought to the conducting state in response to a hierarchical power supply control signal &phgr;c to electrically connect main ground line L
3
and sub-ground line L
4
.
One operation supply node (a node receiving a higher potential) of inverters at the odd number stages X
1
, . . . each is connected to sub-supply line L
2
, and the other operation supply node (a node receiving a lower potential) is connected to main ground line L
3
.
One operation supply node (a node receiving a higher potential) of inverters at the even number stages X
2
, . . . each is connected to main supply line L
1
, and the other operation supply node (a node receiving a lower potential) is connected to sub-supply line L
4
.
Supply potential is applied to main supply line L
1
. Ground potential is applied to main ground line L
3
. Voltage of main supply line L
1
is referred to as voltage Vcc, voltage of sub-supply line L
2
is referred to as voltage SubVcc, voltage of main ground line L
3
is referred to as voltage Vss, and voltage of sub-ground line L
4
is referred to as voltage SubVss.
Referring to
FIGS. 68 and 69
, an operation of the conventional hierarchical power supply system shown in
FIG. 67
is hereinafter described.
FIG. 68
illustrates a timing chart showing variation of supply potential in the conventional hierarchical power supply system shown in
FIG. 67
, and
FIG. 69
is provided for describing voltage conditions of respective inverters X
1
, . . . in a standby cycle.
As shown in
FIG. 69
, inverters X
1
, . . . each include a PMOS transistor P
1
and an NMOS transistor N
1
.
An input signal IN which is brought to an H level and an L level respectively in the standby cycle and an activate cycle is input to the internal circuit illustrated in FIG.
69
. In the standby cycle, control signal &phgr;c is set at the L level. Accordingly, switching transistors T
1
and T
2
are in OFF state in the standby cycle. In the active cycle, control signal &phgr;c is set at the H level.
Upon transition from the active cycle to the standby cycle (at time t
0
and t
2
of FIG.
68
), voltage SubVcc of sub-supply line L
2
gradually decreases from the voltage Vcc level of main supply line L
1
due to the load capacitor. On the other hand, voltage SubVss of sub-ground line L
4
gradually changes to a higher level from voltage (ground supply voltage) Vss of main ground line L
3
due to the load capacitor.
Upon transition from the standby cycle to the active cycle (at time t
1
of FIG.
68
), control signal &phgr;c attains the H level. Accordingly, switching transistors T
1
and T
2
are brought to ON state. Voltage SubVcc of sub-supply line L
2
is charged to the voltage Vcc level of main supply line L
1
. Voltage SubVss of sub-ground line L
4
approaches to the voltage Vss level of main ground line L
3
.
Referring to
FIG. 69
, in the standby cycle, inverter X
2
receives a signal of ground supply voltage Vss which is an inverted one of input signal IN. Accordingly, in inverter X
2
, PMOS transistor P
1
attains ON state, and a connection node between PMOS transistor P
1
and NMOS transistor N
1
is set at voltage Vcc level of main supply line L
1
. Since NMOS transistor N
1
receives voltage SubVcc of sub-ground line L
4
higher than ground supply voltage Vss, the gate voltage becomes smaller than the source voltage. The leakage current in inverter X
2
is thus restricted.
Inverter X
3
receives a signal of voltage Vcc of main supply line L
1
. Accordingly, NMOS transistor N
1
is brought to ON state, and a connection node between PMOS transistor P
1
and NMOS transistor N
1
is set at voltage Vss of main ground line L
3
. Since PMOS transistor P
1
receives voltage SubVcc of sub-supply line L
2
lower than voltage Vcc of main supply line L
1
, the gate voltage becomes higher than the source voltage. Accordingly, the leakage current in inverter X
3
is restricted.
However, in the conventional hierarchical power supply system, as shown in
FIG. 68
, at the instant of transition from the standby cycle to the active cycle, switching transistors T
1
and T
2
are brought into ON state to cause a sudden voltage change of sub-supply line L
2
and sub-ground line L
4
(referred to as voltage drop).
Further, when switching transistor T
1
and T
2
attain ON state, the junction capacitance thereof causes voltage SubVcc of sub-supply line L
2
to become a level slightly lower than voltage Vcc of main supply line L
1
and causes voltage SubVss of sub-ground line L
4
to keep a level slightly higher than voltage Vss of main ground line L
3
.
If the internal circuit operates in this state, a problem arises that an operation feature satisfying a desired condition cannot be obtained and it takes time to define an output from the internal circuit.
In addition, current consumption of a semiconductor integrated circuit device should be effectively decreased according to an operation timing.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor integrated circuit device that can operate with low current consumption and at a high-speed.
The invention further provides a semiconductor integrated circuit device that can operate with low current consumption and at a high-speed according to an operation mode.
The present invention further provides a semiconductor integrated circuit device that can monitor the leakage current to adjust current consumption using the result of the monitoring.
A semiconductor integrated circuit device according to one aspect of the present invention includes a main supply line, a sub-supply line, a coupling circuit for electrically coupling the main supply line and the sub-supply line in an active cycle and for electrically uncoupling the main supply line and the sub-supply line in a standby cycle, a logic circuit having a first logic gate operating with voltage on the main supply line as an operation supply voltage, applying a prescribed logical processing based on a supplied input and outputting a resultant one, and having a second logic gate operating with voltage on the sub-supply line as an operation supply voltage, applying a prescribed logical processing based on a supplied input and outputting a resultant one, and a voltage control circuit for controlling voltage o

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