Bootstrapped charge pump

Details Bootstrapped charge pump Bootstrapped charge pump

2001-05-30

2002-11-05

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S589000, C327S390000

Reexamination Certificate

active

06476666

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to charge pumps and, more particularly, to a cross-coupled, dual-chain charge pump, that is referred here as a bootstrapped charge pump.
2. Description of the Related Art
Historically, semiconductor devices that required voltages that were greater than the power supply voltage utilized dedicated pins to input the required voltages from an off-chip supply. Current-generation non-volatile memory devices, however, commonly use a charge pump, which utilizes the power supply voltage and ground, to generate the required voltages on the chip.
Thus, by utilizing a charge pump, dedicated pins are no longer required to input voltages from an off-chip supply that are greater than the power supply voltage. As a result, the total pin count of a device can be reduced accordingly. This is a significant advantage to current-generation chips that often have a limited number of pins available. Although charge pumps can provide the needed voltages from the power supply voltage and ground, charge pumps typically suffer from a low current drive (can source only a limited amount of current).
FIG. 1
shows a schematic diagram that illustrates a conventional charge pump
100
. As shown in
FIG. 1
, charge pump
100
includes a number of stages SG
1
-SGn that are serially connected together to form a chain. Each stage SG in the chain progressively “pumps” or increases the voltage input to the stage to achieve the needed voltage.
Stages SG
1
-SGn include a corresponding number of input nodes NI
1
-NIn, output nodes NO
1
-NOn, and diode-connected n-channel transistors DN
1
-DNn. Each transistor DN has a gate and drain connected to an input node NI and a source connected to an output node NO. In addition, stages SG
1
-SGn also include a corresponding number of capacitors CAP
1
-CAPn, switching nodes NS
1
-NSn, and switches SW
1
-SWn. Each capacitor CAP is connected between an output node NO and a switching node NS. Each switch SW, in turn, is connected to a switching node NS, and either a power supply voltage VCC or ground, depending on the logic state of a clock signal.
As further shown in
FIG. 1
, first stage SG
1
receives an input voltage VI such as the power supply voltage VCC, while last stage SGn outputs a pumped voltage VPM on output node NOn. The output node NO of each remaining stage is connected to the input node NI of the next stage SG in the chain.
In operation, the switch SW in each odd-numbered stage SG is controlled by a first clock signal PH
1
, while the switch SW in each even-numbered stage SG is controlled by a second clock signal PH
2
that is 180° out-of-phase with the first clock signal PH
1
. For both clock signals PH
1
and PH
2
, when the clock signal is asserted, the switch SW is connected to ground. On the other hand, when the clock signal is de-asserted, the switch is connected to the power supply voltage VCC.
Thus, when the first clock signal PH
1
is asserted, first switch SW
1
is connected to ground. In this condition, the gate-to-source voltage VGS of transistor DN
1
is greater than the threshold voltage VTH
1
of transistor DN
1
. As a result, transistor DN
1
turns on and a current flows from the input node NI
1
to the output node NO
1
until the voltage VO on output node NO
1
rises to a value that is a threshold voltage drop less than the power supply voltage VCC.
When the voltage VO on output node NO
1
is a threshold voltage drop less than the power supply voltage VCC (VO=VCC−VTH
1
), transistor DN
1
turns off as transistor DN
1
conducts only as long as the gate-to-source voltage VGS is greater than the threshold voltage VTH
1
. As a result, the voltage across capacitor CAP
1
is also equal to VCC−VTH
1
.
When the first clock signal PH
1
is de-asserted, switch SW
1
of the first stage SG
1
is connected to the power supply voltage VCC. Since transistor DN
1
is turned off, thereby isolating output node NO
1
from the input node NI
1
, the power supply voltage VCC on switching node SW
1
also appears on output node NO
1
due to the principle of charge neutrality. As a result, the voltage VO
1
on the output node NO
1
is defined in equation EQ. 1 as:
VO
1
=VCC−VTH
1
+
VCC=
2
VCC−VTH
1
.  EQ. 1
Thus, the voltage VO
1
on output node NO
1
is greater by the power supply voltage VCC when the first clock signal PH
1
is de-asserted.
At the same time that the first clock signal PH
1
is de-asserted, the second clock signal PH
2
is asserted which, in turn, causes switch SW
2
to be connected to ground. As with transistor DN
1
, transistor DN
2
turns on until the voltage VO
2
on output node NO
2
is a threshold voltage drop less than the voltage on input node NI
2
/output node NO
1
.
The voltage VO
2
on output node NO
2
takes several clock cycles to reach 2VCC−VTH
1
−VTH
2
. This is because, unlike transistor DN
1
where the current is delivered from the power supply voltage VCC, the current flowing into the output node NO
2
from input node NI
2
/output node NO
1
reduces the voltage on input node NI
2
/output node NO
1
, and thus, additional cycles are needed for the nodes to reach their full potentials.
When the second clock signal PH
2
is de-asserted, switch SW
2
is connected to the power supply voltage VCC which, in turn, causes the voltage VO
2
on output node NO
2
to be increased by the power supply voltage VCC. This process continues as described above. Thus, charge pump
100
shifts electrons from the output node NO to the input node NI of each stage SG until the pumped voltage VPM on output node NOn is equal to:
VPM=n
(
VCC
)−(
VTH
1
+VTH
2
+ . . . +VTHn
).  EQ. 2
(The pumped voltage VPM is actually slightly less due to the body effect of the transistors DN in each stage SG.)
One disadvantage of charge pump
100
is that the pump voltage VPM is reduced by the combined threshold voltage drops (VTH
1
+VTH
2
+ . . . +VTHn). The transistors in the charge pump, being configured as diodes, do not act as ideal switches, as in the case of an ideal charge pump. Further, the drive strength of the pump is greatly reduced when current is drawn from the pump. In some cases, an additional stage SG may need to be added to compensate for this loss, thereby increasing the size and cost of the charge pump. Thus, there is a need for a charge pump that outputs a pumped voltage VPM that is not reduced by the accumulated threshold voltage drops.
SUMMARY OF THE INVENTION
The charge pump of the present invention outputs a pumped voltage that is not reduced by the accumulated threshold voltage drops by utilizing a dual-chain charge pump where the pumped voltages from each charge pump chain drive the gates of the other charge pump chain. As a result, the voltages on the gates of the transistors are pumped up to be at least one diode drop greater than the voltages on the drains of the n-channel transistors, and one diode drop less than the voltages on the sources of the p-channel transistors.
In the charge pump of the present invention, the diode drops associated with the transistors are eliminated as a result of the pumped voltages on the drains/sources of the transistors of each pump that gets coupled to the gates of the transistors of the other pump. This makes the transistors act as ideal switches, and thus, enables the voltages on the sources/drains of the transistors to reach their full potentials, without being limited by their threshold voltages. Thus, this cross-coupled charge pump exhibits a bootstrapping phenomena, as the sources/drains are bootstrapped to reach their full potentials. Hence, the charge pump of the present invention is referred to as a bootstrapped charge pump.
A charge pump stage in accordance with the present invention includes a bottom transistor and a top transistor. The bottom transistor has a first node, a gate, and a second node. The top transistor has a third node, a gate connected to the second node of the bottom transistor, and a sec

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