Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-03-07
2002-11-12
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S088000, C345S206000, C345S211000, C345S213000, C330S252000, C330S261000, C330S295000, C330S300000, C330S110000, C257S072000, C438S149000, C438S150000, C438S151000, C438S152000, C438S153000
Reexamination Certificate
active
06480179
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates particularly to an image display device including a high-gain high-performance voltage amplifier circuit comprised of polycrystalline field effect transistors.
A prior art TFT (Thin Film Transistor) liquid crystal display device will be explained by reference to
FIGS. 10
,
11
and
12
.
FIG. 10
shows a circuit configuration formed on a transparent insulating substrate (not shown) for the TFT liquid crystal display device. A pixel comprises a liquid crystal capacitance
202
and a pixel switch
201
comprised of a polycrystalline semiconductor TFT. A gate of the pixel switch
201
is driven by a gate line scanning register
205
via a gate line
204
. A drain of the pixel switch
201
is connected to an output buffer
206
via a signal line
203
. An analog signal input line
212
is connected to a signal sampling capacitance
210
via a signal sampling switch
211
, and is also inputted to an output buffer
206
via a signal hold switch
208
and a signal hold capacitance
207
. The signal sampling switch
211
is controlled by a signal sampling register
213
, and the signal hold switch
208
and the output buffer
206
are controlled by a signal hold line
209
.
Next, the operation of the above prior art device will be explained. An analog video signal from the analog signal input line
212
is stored in the signal sampling capacitance
210
via the signal sampling switch
211
successively scanned by the signal sampling register
213
. After the pixel signals constituting a scanning line have been stored in the respective signal sampling capacitances
210
, they are transferred to the respective signal hold capacitances
207
via the respective signal hold switches
208
in synchronism with a clock signal from the signal hold line
209
during a horizontal blanking period and then are inputted to the respective output buffers
206
. The output buffers
206
supply outputs having magnitudes according to the input signals to the signal lines
203
. At this time the gate line scanning register
205
is driven to select a predetermine one of the gate lines
204
such that a row of the pixel switches
201
corresponding to the scanning line become conducting, and as a result the output signals supplied to the signal lines
203
are written into the liquid crystal capacitances
202
.
FIG. 11
is a cross-sectional view of a structure of the pixel switch
201
. A channel region is formed by an i region
224
, an n
−
region
225
and an i region
226
, and a source
223
and a drain
227
are formed by p
+
regions on opposite sides of the channel region, respectively. The channel region, the source and the drain are made of polycrystalline semiconductor films. The gate electrode
221
is disposed over the channel region with an insulating film
222
interposed therebetween. Such a prior art pixel switch
201
disposes an n
−
region
225
in the channel region to form a pin junction in the reverse direction comprised of the drain
227
, the n
−
region
225
and an i layer sandwiched therebetween and thereby reduces a leakage current in its OFF state. Such a prior art technique is disclosed in detail by Japanese Patent Application Laid-open No. Hei 8-32069 (laid-open on Feb. 2, 1996).
Japanese Patent Application Laid-open No. Hei 8-32069 also discloses a technique of forming an output buffer
206
of the peripheral circuit by polycrystalline semiconductor TFTs a cross-sectional view of one of which is shown in FIG.
12
. This TFT employs an LDD (Lightly Doped Drain) structure. The reason that this TFT differs in structure from the transistor of the above-explained pixel switch
201
is that high-speed operation is required of this transistor rather than the reduction of the leakage current. An i region
235
forms a channel region, two pairs of a combination of n
+
and n
−
regions on opposite sides of the channel region form a source
233
and
234
and a drain
237
and
236
, respectively. These i, n
+
and n
−
regions are formed of polycrystalline semiconductor films. A gate electrode
231
is disposed over the channel region with an insulating film
232
interposed therebetween.
SUMMARY OF THE INVENTION
But, when the output buffer
206
is formed by the polycrystalline TFTS, as is apparent from a current-voltage characteristic of this TFT shown in
FIG. 13
, it was found that, when a drain voltage Vds exceeds a pinch-off voltage VA, a phenomenon of rapid increase in drain current occurs in which an actual value
241
of a drain current Ids increases to a considerably larger current than an intrinsic saturation current value
242
.
The cause for occurrence of this phenomenon can be thought of as the following. Electron-hole pairs are generated by impact ionization in the boundary region between the i region
235
and n
−
region
236
because a comparatively high electric field is applied across the boundary between the i region
235
and n
−
region
236
shown in FIG.
12
. The generated holes moves toward the source
234
experiencing pair annihilation with the electrons in the channel, concentration of the holes increases in the channel in the vicinity of the drain
236
during this process and consequently the channel potential of this region is lowered. As a result, an apparent threshold voltage Vth in the vicinity of the drain
236
is decreased when the drain voltage is raised and consequently the drain current increases by a current component corresponding to the hole-generated current.
The above-explained phenomenon of rapid increase in drain current adversely effects the output buffers
206
generally formed by a negative feedback amplifier. The output buffer
206
must be designed to provide a sufficiently large amplifier gain so as to secure its good linearity, but the above phenomenon increases drain conductance extraordinarily and this makes the design of a high-gain amplifier very difficult.
It is an object of the present invention to provide an image display device employing a voltage amplifier circuit such as an output buffer comprised of a TFT with occurrence of the phenomenon of rapid increase in drain current being suppressed.
To accomplish the above object, in accordance with an embodiment of the present invention, there is provided an image display device comprising an image display section including an insulating substrate having a matrix of pixels formed on an inner surface thereof and a liquid crystal layer sandwiched between the insulating substrate and a substrate opposing the insulating substrate comprising: a plurality of signal lines; a plurality of driver circuits for driving the matrix of pixels via the signal lines; a plurality of voltage amplifiers formed by polycrystalline semiconductor TFTs and each coupled between one of the signal lines and a corresponding one of the driver circuits; the signal lines, the driver circuits and the voltage amplifiers being formed on a surface of the insulating substrate on a side thereof facing the liquid crystal layer, wherein a channel, a source and a drain of the polycrystalline semiconductor TFTs each are formed of a polycrystalline semiconductor film, a gate insulating film and a gate electrode are superposed on the polycrystalline semiconductor film in the order named, and the polycrystalline semiconductor TFTs are provided with a second region of the channel having a threshold voltage higher than a threshold voltage of a first region of the channel on a drain side thereof.
REFERENCES:
patent: 5372836 (1994-12-01), Imahashi et al.
patent: 6096581 (2000-08-01), Zhang et al.
patent: 6210997 (2001-04-01), Adachi et al.
patent: 6252215 (2001-06-01), Mei et al.
patent: 6306694 (2001-10-01), Yamazaki et al.
patent: 6333520 (2001-12-01), Inoue
patent: 8-32069 (1996-02-01), None
Hitachi , Ltd.
Hjerpe Richard
Mattingly Stanger & Malur, P.C.
Zamani Ali
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