Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2001-06-26
2002-12-17
Vu, David (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C345S060000, C345S063000
Reexamination Certificate
active
06495968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving a plasma display panel.
2. Description of Related Art
In recent years, display devices have been required to provide reduced thickness as the devices have been increased in size, and accordingly various types of thin display devices have been in practical use. Attention is focused on an AC discharge plasma display panel as one of the thin display devices.
FIG. 1
is a schematic view illustrating the configuration of a plasma display device comprising such a plasma display panel and a drive device.
Referring to
FIG. 1
, the plasma display panel or a PDP
10
comprises m column electrodes D
1
to D
m
, and n row electrodes X
1
to X
n
and n row electrodes Y
1
to Y
n
, each of which intersects the column electrodes. These row electrodes X
1
to X
n
and row electrodes Y
1
to Y
n
allow a pair of row electrode X
i
(1≦i≦n) and row electrode Y
i
(1≦i ≦n) to form the first to nth display line in the PDP
10
. In between a column electrode D and row electrodes X, Y, there is formed a discharge space in which a discharge gas is sealed. There is formed a display cell acting as a pixel at the intersection of each pair of row electrodes and a column electrode, including the discharge space.
With this construction, each display cell emits light through a discharge phenomenon and therefore has only two states, or a “light-emitting” state and a “non-light-emitting” state. Accordingly, the display cell can express the brightness of only two levels of gray scale, or a minimum brightness (“non-light-emitting” state) and a maximum brightness (“light-emitting” state).
In this regard, for the implementation of displaying halftone brightness corresponding to an input video signal, a driver
100
employs a subfield method to perform gray scale drive on the PDP
10
mentioned above.
According to the subfield method, for example, an input video signal is converted into display data of four bits corresponding to each display cell. As shown in
FIG. 2
, one field comprises four subfields SF
1
to SF
4
corresponding to each bit digit of the four bits. Then, in each of the subfields, as described below, a simultaneous reset process Rc, a data write process Wc, a light-emission sustain process Ic, and an erase process E are performed, respectively.
FIG.
3
. is a view illustrating various types of drive pulses that the driver
100
applies to the aforementioned PDP
10
, and the application timing of the drive pulses.
First, in the aforementioned simultaneous reset process Rc, the driver
100
applies a positive reset pulse RP
X
to the row electrodes X
1
to X
n
and a negative reset pulse RP
Y
to the row electrodes Y
1
to Y
n
. The application of these reset pulses RP
X
and RP
Y
will cause all display cells of the PDP
10
to be reset and discharged, allowing a predetermined uniform wall charge to be built in each of the display cells. Immediately thereafter, the driver
100
applies simultaneously an erasing pulse EP to the row electrodes X
1
to X
n
of the PDP
10
. The application of the erasing pulse EP will cause an erase discharge to be generated in all of the display cells, thereby erasing the aforementioned wall charge. This will reset all the display cells to the state in which no light emission (sustain discharge) is allowed (hereinafter referred to as the “non-light-emitting cell” state) in the light-emission sustain process Ic, described later.
Then, in the data write process Wc, the driver
100
separates each bit of the aforementioned display data of four bits corresponding to each of the subfields SF
1
to SF
4
to generate a data pulse having a pulse voltage corresponding to the logic level of the bits. For example, in the data write process Wc of the subfield SF
1
, the driver
100
generates a data pulse having a pulse voltage corresponding to the logic level of the first bit of the aforementioned display data. At this time, the driver
100
generates a high-voltage data pulse with the logic level of the first bit being “1”, and a low-voltage (zero volt) data pulse with the logic level being “0”. Then, as shown in
FIG. 3
, the driver
100
successively applies such data pulses to the column electrodes D
1
to D
m
as a group of data pulses DP
1
to DP
n
for each display line corresponding to each of the first to nth display lines. Furthermore, as shown in
FIG. 3
, the driver
100
generates a negative scanning pulse SP in phase with the application timing of each group of data pulses DP to apply successively the negative scanning pulse SP to the row electrodes Y
1
to Yn. At this time, discharge (selective write discharge) is caused only at the display cells located at the intersections of the display lines to which the scanning pulse SP is applied and the “columns” to which the high-voltage data pulse is applied. After such a selective write discharge has been terminated, wall charges are built up in the display cells and held. This causes the display cells that have been reset to the “non-light-emitting cell” state in the aforementioned simultaneous reset process Rc to change to the state (hereinafter referred to as the “light-emitting cell” state) in which the display cells can emit light (sustain discharge) in the light-emission sustain process Ic, described later. On the other hand, no such a selective write discharge described above is generated in the display cells to which the scanning pulse SP or the low-voltage data pulse has been applied, allowing the state that has been reset in the aforementioned simultaneous reset process Rc or the “non-light-emitting cell” state to be held.
Subsequently, as shown in
FIG. 3
, in the light-emission sustain process Ic, the driver
100
applies the positive sustain pulse IPX and the positive sustain pulse IP
Y
alternately to the row electrodes X
1
to X
n
and the row electrodes Y
1
to Y
n
, respectively. Incidentally, as shown in
FIG. 2
, the number of times (or the duration) of application of the sustain pulses IP
X
and IP
Y
in one subfield is set according to the weight of each subfield. Here, only the display cells in which wall charges are present or only the display cells in the “light-emitting cell” state perform sustain discharge every time the aforementioned sustain pulses IP
X
and IP
Y
are applied thereto in order to sustain the “light-emitting” state involved in the discharge.
Subsequently, in the erase process E, the driver
100
applies simultaneously the negative erasing pulse EP, shown in
FIG. 3
, to each of the row electrodes Y
1
to Y
n
. This allows an erase discharge in all the display cells to be generated, causing all the wall charges remaining in each of the display cells to dissipate.
Execution of the series of these operations in each of the subfields (SF
1
to SF
4
) will allow halftone brightness to be viewed in accordance with the total number of times of light emission carried out in the light-emission sustain process Ic of each subfield. For example, for the four subfields as mentioned above, it is possible to express the range of brightness available to an input video signal with 16 levels of halftone brightness by combining the subfields that are allowed to emit light in the light-emission sustain process Ic. At this time, the greater the number of subfields to be provided by division, the greater the number of steps or the level of gray scale becomes, thereby making it possible to provide a display image of higher quality.
However, since the display period of one field is specified, the number of subfields provided by dividing a field cannot be increased without limitation.
In addition, in the drive shown in
FIGS. 2 and 3
, a light emission pattern for providing display brightness of brightness level “7” shown in
FIG. 4
is inverted with respect to that for providing display brightness of brightness level “8” in one field period. In some cases, this would cause false contours to be viewed in the image.
That is, as shown in
FIG. 4
, the display cells for displaying b
Lee Wilson
Pioneer Corporation
Vu David
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