Static information storage and retrieval – Powering
Reexamination Certificate
2000-12-29
2002-12-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
C365S063000
Reexamination Certificate
active
06498759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a type of motherboard. More particularly, the present invention relates to a motherboard system capable of producing a suitable voltage source to power synchronous dynamic random access memory (SDRAM) and double-data-rate dynamic random access memory (DDR DRAM).
2. Description of Related Art
At present, most personal computers use synchronous dynamic access memory (SDRAM) for program and data storage. Since SDRAM responds to the rising edge of a system clock, operations are triggered by the rising edge of a clock cycle only. Following recent advances in semiconductor technology, another type of memory known as double-data-rate DRAM (DDR DRAM) is introduced into the market. DDR DRAM responds to both the rising and the falling edge of a system clock, and hence the operating speed of memory is almost doubled.
The operating modes of SDRAM and DDR DRAM are different in many aspects, including; (1) SDRAM uses normal clock pulse signals while DDR DRAM uses differential clock signals; (2) SDRAM uses V
DD
=3.3V while DDR DRAM uses V
DD
=2.5V and V
DDQ
=2.5V; (3) SDRAM does not require a reference voltage, but DDR DRAM requires a reference voltage whose value is about ½ V
DDQ
; (4) SDRAM connects to a data bus that operates on CMOS logic while DDR DRAM connects to a data bus that operates on series-stub-terminated logic 2 (STTL
—
2); (5) there is no need for the SDRAM connected data bus connected to use a terminated voltage (V
TT
), but DDR DRAM connected to data bus must use a terminated voltage (V
TT
) to absorb reflected waves; and (6) there is no need for the SDRAM connected to data bus to use a pull-up resistor, but the DDR DRAM connected to data bus must use a pull-up resistor. However, a DDR DRAM is able to operate at a speed roughly double that of the SDRAM.
Due to the aforementioned differences between SDRAM and DDR DRAM, particularly to the power requirements, inappropriate provision of power supply can pin to severe problems. For example, if DDR DRAM modules are plugged into the slots on a motherboard, the memory modules may be burnt if the power supply provides a 3.3 V. Alternatively, if SDRAM modules are plugged into the slots on a motherboard, the memory modules may not operate normally if the power supply only provides a 2.5V voltage source.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a system on a motherboard capable of automatically providing a 2.5V voltage source to power DDR DRAM modules and a 3.3V voltage source to power SDRAM. Consequently, consumers do not have to worry about burning the memory modules or memory malfunction due to a difference in operating voltages between the two types of memory modules.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied arid broadly described herein, the invention provides an automatic voltage generation system on a motherboard. The system includes a general-purpose input/output port, a memory module slot and a power safety device. The memory module slot is used for accommodating a memory module. The power safety device is coupled to the general-purpose input/output port and the memory module slot. According to the output from the general-purpose input/output port of a chipset, the power source pin of the power safety device outputs a 3.3V when SDRAM is plugged into the memory module slot. Alternatively, the power source pin of the power safety device outputs a 2.5V when DDR DRAM is plugged into the memory module slot.
The motherboard further includes a central processing unit (CPU) and the memory module further includes an electrical erasable programmable read-only-memory (EEPROM) for recording related data indicating the memory module When the system is boot up, the CPU is able to read the related data recorded in the EEPROM through a chipset and recognize the type of memory module plugged into the slots and control the output from the general-purpose input/output port. Therefore, the power safety device is able to determine whether to supply a 3.3V or a 2.5V to the voltage source pin automatically.
The power safety device further includes a first flip-flop, a second flip-flop, a first field effect transistor and a second field effect transistor. The first flip-flop has a first input terminal, a second input terminal and a positive phase output terminal. The first input terminal of the first flip-flop receives output from the general-purpose input/output port and the second input terminal of the first flip-flop receives signal from a power-good signal supplier The second flip-flop has a first input terminal, a second input terminal and a negative phase output terminal. The first input terminal of the second flip-flop receives output from the general-purpose input/output port and the second input terminal of the second flip-flop receives signal from a power-good signal supplier. The first field effect transistor has a gate electrode, a first source/drain electrode and a second source/drain electrode. The gate electrode of the first field effect transistor is coupled to the positive phase output terminal of the first flip-flop and a +12V voltage source via a first resistor. The first source/drain electrode of the first field effect transistor is coupled to a 3.3V voltage source and the second source/drain is electrode of the first field effect transistor is coupled to the voltage source pin. The second field effect transistor has a gate electrode, a first source/drain electrode and a second source/drain electrode, The gate electrode of the second field effect transistor is coupled to the negative phase output terminal of the second flip-flop and a +12V voltage source via a second resistor. The first source/drain electrode of the second field effect transistor is coupled to a 2.5V voltage source and the second source/drain electrode of the second field effect transistor is coupled to the voltage source pin.
On starting the computer system, the power-good signal causes the second source/drain electrode of the second field effect transistor to output 2.5V to the voltage source pin. If the memory module slot contains a SDRAM module, output from the general-purpose input/output port causes the second source/drain electrode of the first field effect transistor to output 3.3V to the voltage source pin. On the other hand, if the memory module slot contains a DDR DRAM module, the 2.5V output to the voltage source pin is maintained. In brief, the power safety device is able to output 3.3V or 2.5V to the voltage source pin automatically according to the type of memory module plugged into the memory slot.
The power safety device can also provide a low-current pulse to the reference voltage source pin of the memory module slot. By checking if any fluctuation in the low-current pulse exceeds a pre-defined range, a current one of SDRAM or DDR DRAM being plugged into the memory module slot can be determined. According to the type of memory modules plugged into the slots, a 3.3V or a 2.5V is automatically put on the voltage source pin.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Chang Nai-Shung
Chuang Ching-Fu
Ho Hsiu-Wen
J. C. Patents
Nelms David
Nguyen Thinh T
VIA Technologies Inc.
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