Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
1999-12-06
2002-12-31
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S203000
Reexamination Certificate
active
06501106
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices and methods of producing the same, and, more particularly, to a wiring pattern of a wiring layer in a semiconductor integrated circuit device having aligned basic cells and logic unit cells each made up of basic cells.
In recent years, the number of gates has been increasing even further in a master-slice-type semiconductor integrated circuit device (gate array) having aligned basic cells or in a complex LSI in which basic cells do not coexist with a standard cell, a CPU core, or an analog circuit. Because of this, logic unit cells made up of basic cells are formed as many as possible in the center of such a semiconductor integrated circuit device. Such logic unit cells are connected to one another.
As the number of logic unit cells arranged in the center of a semiconductor integrated circuit device has become larger, the wiring pattern for connecting the logic unit cells has become more complicated. Because of this, the wiring operation is becoming more and more time-consuming and troublesome. Also, a large number of basic cells are often left unused, while each semiconductor integrated circuit device is becoming larger in size.
2. Description of the Related Art
As shown in
FIG. 1
, a plurality of basic cells
52
in a lattice arrangement in X and Y directions are formed in the center of a conventional semiconductor integrated circuit device
51
. Each of the basic cells
52
has a rectangular shape, with its long side being &agr; and its short side being &bgr; in FIG.
1
.
Each of the basic cells
52
shown in
FIG. 2
comprises a P
+
-type diffused region
53
, an N
+
-type diffused region
54
, and gate electrodes
55
made of polycrystalline silicon. In each of the basic cells
52
, p-channel MOS transistors
56
and
57
, and n-channel MOS transistors
58
and
59
are formed as shown in FIG.
3
.
To form a logic unit cell such as a NAND circuit or a flip-flop, a plurality of basic cells
52
are used to retain a necessary number of transistors
56
to
59
. The basic cells
52
arranged in the X-direction are connected to form a logic unit cell
61
shown in FIG.
4
. Here, the X-direction is an extending direction.
To form the logic unit cell
61
, connections within each basic cell
52
and between the basic cells
52
are made by first-layer wiring regions (a lower wiring layer). In a case where the first-layer wiring regions are not enough to form the logic unit cell
61
, second-layer wiring regions (an upper wiring layer)
71
are used. As shown in
FIGS. 4 and 5
, such second-layer wiring regions
71
are formed in the Y-direction within each logic unit cell
61
.
In a case where one logic unit cell
61
is connected to another logic unit cell
61
disposed in the Y-direction as shown in
FIG. 5
, second-layer wiring regions (the upper wiring layer)
76
extending in the Y-direction in each logic unit cell
61
are used. Such second-layer wiring regions
76
are employed so as to extend the logic unit cells
61
in the Y-direction.
The number of basic cells
52
included in each of the logic unit cells
61
varies from one another. Accordingly, as shown in
FIG. 5
, the positions of the second-layer wiring regions
71
formed in the X-direction in the lower logic unit cell
61
scarcely coincide with the positions of the second-layer wiring regions
71
formed in the X-direction in the upper logic unit cell
61
. Also, the short side &agr; of each basic cell
52
extends in the X-direction, and is too short to match the positions of the second-layer wiring regions
71
and
76
in the X-direction.
As a result, the second-layer wiring regions
71
hinder formation of the second-layer wiring regions
76
for connecting the logic unit cells
61
in the Y-direction. To avoid this, the logic unit cells
61
are shifted from each other in the X-direction, as shown in FIG.
4
. However, by shifting the logic unit cells
61
from one another, idle spaces
80
are created, and the basic cells
52
existing within the idle spaces
80
are left unused. Accordingly, it is necessary to add more gates for those unused basic cells
52
, resulting in a larger semiconductor integrated circuit device.
Furthermore, it is time-consuming and troublesome to design the wiring pattern in such a manner that the second-layer wiring regions
71
formed within each logic unit cell
61
do not hinder the formation of the second-layer wiring regions
76
for connecting the logic unit cells
61
in the Y-direction.
SUMMARY OF THE INVENTION
A general object of the present invention is to provide a semiconductor integrated circuit device in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor integrated circuit device in which connections within each logic unit cell and between logic unit cells can be easily made without leaving any basic cell unused, and a method of producing such a semiconductor integrated circuit device.
The above objects of the present invention are achieved by a semiconductor integrated circuit device comprising: basic cells in a lattice arrangement, with one direction being an extending direction; logic unit cells each including the basic cells in the extending direction; and second-layer wiring regions formed in the extending direction within each of the logic unit cells, the second-layer wiring regions in the extending direction being fixed in predetermined positions.
Accordingly, the second-layer wiring regions for connecting the logic unit cells in the extending direction can be formed in positions other than the predetermined positions for the second-layer wiring regions within each of the logic unit cells. Thus, more flexibility can be allowed in forming the second-layer wiring regions for connecting the logic unit cells in the extending direction. Accordingly, idle spaces, i.e., the number of unused basic cells can be reduced, thereby achieving higher integration in the semiconductor integrated circuit device.
Also, the positions of the second-layer wiring regions for connecting the logic unit cells do not include any the predetermined positions, so as not to interfere with the second-layer wiring regions for making connections within each logic unit cell. Thus, the workability in designing the wiring pattern in the semiconductor integrated circuit device can be improved.
In the semiconductor integrated circuit device of the present invention, a plurality of second-layer wiring regions may be formed within each logic unit cell. In such a case, order of priority is set on the formation positions of the second-layer wiring regions within each logic unit cell. Accordingly, the second-layer wiring regions are formed in the order of priority. In this manner, it is easy to determine which formation positions are already occupied or not from the order of priority. The second-layer wiring regions for connecting the logic unit cells are formed in positions other than the formation position determined to be occupied. Thus, the workability in designing the wiring pattern in the semiconductor integrated circuit device can be greatly improved.
The above and other objects and features of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5986294 (1999-11-01), Kiki et al.
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Potter Roy
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