Low voltage supply higher efficiency cross-coupled high...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Reexamination Certificate

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06501325

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for charge pumps generally and, more particularly, to a method and/or architecture for low voltage supply high efficiency cross-coupled high voltage charge pumps.
BACKGROUND OF THE INVENTION
Charge pumps are circuits that pump charge into capacitors to develop an output voltage higher than the supply voltage. High voltage charge pumps provide positive or negative high voltage to program/erase programmable elements such as EEPROM and flash memory, power solid-state particle detectors and photo-multipliers, drive analog switches, etc. Multiple charge pump circuits can be implemented serially to increase the voltages provided. Conventional charge pump circuits include a number of serially connected stages. The stages contain a diode (or transistor configured as a diode) and a capacitor. The stages are driven by a clock signal.
Referring to
FIG. 1
a,
a diagram of a circuit
10
illustrating a conventional charge pump is shown. The circuit
10
illustrates a so-called Dickson charge pump circuit (see J. F. Dickson, “On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique”, IEEE J. of Solid-state Cir., vol SC-11, No. 3, June, 1976, pp. 374-378, which is hereby incorporated by reference in its entirety). The circuit
10
includes a number of stages
12
a
-
12
n.
Each stage
12
contains a diode connected transistor
14
and a capacitor
16
.
The circuit
10
can provide a supply voltage minus threshold voltage (Vcc−Vt) increase at each stage. The output voltage Vpp of the circuit
10
can be Vpp=(Vcc−Vt)*n+Vcc. However, the amplitude of clock pulses &phgr;a and &phgr;b, pump capacitance (Cp), stage parasitic capacitance (Cs), and load current (Io) are factors that can limit the voltage gain achieved at each pump stage.
For charge to be passed fully from a lower stage to a higher stage, the increase in voltage for the stage &Dgr;Vstage must be greater than the transistor threshold voltage Vt. The circuit
10
has a number of disadvantages. For example, (i) the diode drop reduces efficiency, (ii) the breakdown voltage of the transistors must increase as charge pump output voltage increases, (iii) extra stages are required due to low efficiency, (iv) an output voltage at least one Vt above the desired output voltage must be developed, and (v) the circuit
10
does not work well at low supply voltage levels.
Referring to
FIG. 1
b,
a diagram of a circuit
20
illustrating another conventional charge pump is shown. A description of the circuit
20
can be found in Jieh-Tsong Wu and Kuen-Long Chang, “MOS Charge Pumps for Low-Voltage Operation”, IEEE J. of Solid-state Cir., Vol. 33, No. 4, April, 1998, pp 592-597, which is hereby incorporated by reference in its entirety. The circuit
20
is implemented similarly to the circuit
10
of
FIG. 1
a.
However, to improve low supply voltage performance, each stage
22
of the circuit
20
has an additional transistor
28
. The circuit
20
is more efficient than the circuit
10
and eliminates the voltage threshold Vt drop. However, the circuit
20
has disadvantages in that (i) the charge can flow backwards when the clock signals &phgr;a and &phgr;b transition low at each corresponding stage and (ii) the circuit
20
must develop an output voltage that is at least one Vt higher than the required output voltage Vpp.
Referring to
FIG. 1
c,
a diagram of a circuit
30
illustrating another conventional charge pump circuit is shown. A description of the circuit
30
can be found in Jieh-Tsong Wu and Kuen-Long Chang, “Low Supply Voltage MOS Charge Pumps”, 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp 81-82, which is hereby incorporated by reference in its entirety. In order to eliminate the charge backflow problem of the circuit
20
of
FIG. 1
b,
a charge transfer switch circuit
40
is added at each stage
32
a
-
32
(n−1). The circuit
30
has an advantage when compared to the circuit
20
that charge is always pumped forward. However, the circuit
30
has the disadvantages of (i) an output voltage that must be at least one Vt above the desired output voltage and (ii) the transistors and capacitors at the stages
32
n−
1 and
32
n
must have a high breakdown voltage (breakdown voltage=Vpp+Vt where Vt can be as high as 3V).
It would be desirable to have a charge pump circuit that can efficiently develop a high positive or negative output voltage from a low input voltage without requiring higher breakdown voltage transistors.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a number of cross-coupled charge pump stages configured to generate an output voltage in response to (i) a supply voltage, (ii) a first signal, and (iii) a second signal, where the output voltage has a greater magnitude than the supply voltage.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a low voltage supply higher efficiency cross-coupled high voltage charge pump that may (i) have improved efficiency, (ii) have reduced diode drop, (iii) perform well at low supply voltages, (iv) reduce the need for higher breakdown voltage transistors, (v) require little extra die area, and/or (vi) be easily implemented.


REFERENCES:
patent: 5943226 (1999-08-01), Kim
patent: 6107864 (2000-08-01), Eukushima et al.
patent: 6198340 (2001-03-01), Ting et al.
patent: 6278315 (2001-08-01), Kim
patent: 6404270 (2002-06-01), Meng
Meng, Anita, “Switched Well Technique for Biasing Cross-Coupled Switches or Drivers”, Ser. No. 09/723,494, Filed Nov. 28, 2000.
Meng, Anita, “Bi-Directional Architecture for a High-Voltage Cross-Coupled Charge Pump”, Ser. No. 09/828,772, Filed Apr. 9, 2001.
“On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique”, IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 374-378.
“Low Supply Voltage CMOS Charge Pumps”, By Jieh-Tsorng Wu et al., 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 81-28.
“MOS Charge Pumps for Low-Voltage Operation”, By Jieh-Tsorng Wu et al., IEEE Journal of Solid-State Circuits, vol. 33, No. 4, Apr. 1998, pp. 592-597.
“A New Charge Pump Without Degradation in Threshold Voltage Due to Body Effect”, By Jongshin Shin, et al., IEEE Journal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000, pp. 1227-1230.
“Floating-Well Charge Pump Circuits for Sub-2.0V Single Power Supply Flash Memories”, By Ki-Hwan Choi, 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 61-62.
“A Dynamic Analysis of the Dickson Charge Pump Circuit”, By Toru Tanzawa et al., IEEE Journal of Solid-State Circuits, Vo. 32, No. 8, Aug. 1997, pp. 1231-1240.

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