Correcting method of exposure pattern, exposure method,...

Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement

Reexamination Certificate

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C430S005000

Reexamination Certificate

active

06492078

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a correcting method of exposure pattern, an exposure method, an exposure system, a photomask and a semiconductor device.
2. Description of the Related Art
In the case of preparing a photomask having a light shielding film pattern, prior to a manufacturing process of a semiconductor device, computer-aided design (CAD) data relative to an exposure pattern having a previously designed light shielding film pattern is converted into data for lithography system. Subsequently, patterning is faithfully carried out by the lithography system on the basis of the above data for lithography system so as to generate an exposure pattern having the light shielding film pattern thus prepared. Then, the exposure pattern is transferred onto a glass substrate using a photographic technology so as to generate a photomask having the exposure pattern.
In the manufacturing process of a semiconductor device, the exposure pattern on the photomask is projected on a semiconductor wafer, on which a photosensitive thin film is previously formed, by using a pattern transfer technology such as a so-called photolithography. Then, the photosensitive thin film is exposed by light and is then developed. Thus, a resist pattern faithfully following a shape of the light shielding film is generated on the semiconductor wafer.
Reference document:
“Illustrated Ultra-LSI Optics (Zukai Cho-LSI Kogaku)” published by Tetsugaku Shuppan (K.K.)
In this photolithography process in the manufacturing process of a semiconductor device, a resist pattern having a pattern width near a wavelength of light used for exposure is formed on a semiconductor wafer, and an interference effect of light remarkably appears in the exposure. As a result, a defect by optical proximity effect becomes a problem. Specifically, the optical proximity effect is a factor in causing a dimensional error between a pattern prepared in making a design and the resist pattern that uses the prepared pattern and is generated on the semiconductor wafer in the aforesaid manner using the pattern.
The defect by optical proximity effect appears as an enlargement phenomenon of a width of resist pattern occurring between a plurality of resist line patterns which are formed by being repeatedly arranged, and as a line shrinkage phenomenon occurring in an end portion of an isolated resist pattern. For this reason, in a manufacturing process of the semiconductor device, there is the possibility of causing problems such as a deterioration of gate line width control and a reduction of margin in alignment.
In a semiconductor device manufactured by the manufacturing process having the problem as described above, a dispersion increases in a transistor characteristic, and finally, the yield is reduced. As a result, there is the possibility of remarkably giving an influence to a productivity of a semiconductor chip.
The aforesaid problem is a fatal factor in a manufacturing process of a repeated memory cell requiring a high integration. In order to solve the above problem, after generation of device manufactured by a manufacturing process based on a design by 0.35 &mgr;m rule, there is a need for exposing a pattern width in the vicinity of exposure wavelength of a light used in exposing on a semiconductor wafer. For this reason, a high, accurate optical proximity effect automatic correction (hereinafter, referred simply to as OPC) system based on a light intensity simulation has been developed.
After generation of manufacturing a semiconductor device on the basis of a design by 0.35 &mgr;m rule, the defect resulting from the optical proximity effect appears as the following phenomena. The phenomena includes a dispersion of a line width of a line pattern arranged and formed in not only repeated memory cell area but also one chip random circuit IC area generated by an ASIC (application specific IC) type semiconductor device such as gate array or the like, and a line shrinkage occurring in an end portion of an isolated resist pattern. Finally, the yield is reduced. As a result, there is a problem of remarkably giving an influence to a productivity of a semiconductor IC chip.
In the aforesaid random circuit IC, in order to correct the optical proximity effect in a random pattern formed into a one-chip scale, the OPC system based on light intensity simulation is applied. However, in this case, the following problems arise. Specifically, a huge calculating time for calculating the correction data is required, and there is an influence of increasing of the number of days required for TAT (turn-around time) from design to manufacturing processes of a semiconductor chip.
For example, a required time for making a correction for each cell unit of about several pm angle is about 10 seconds. However, about several hundreds of days are required in the case of correcting all of defects resulting from the optical proximity effect for each cell unit of the entire semiconductor chip.
In order to solve the problem of requiring a huge required time, the following method has been known as a proper method. Specifically, there is a rule base method of correcting the defect of only limited pattern of the entire IC chip on the basis of a previously set rule. However, at present, this method has no level of making a perfectly satisfied correction on defect.
Next, with reference to
FIGS. 4A and B
,
FIGS. 5A and B
and
FIG. 8
, the following examples will be described. More specifically, there are shown light intensity simulation results of an influence of an optical proximity effect resulting from a coarse and dense dependency of pattern array, and of correcting a pattern receiving the optical proximity effect by using a conventional method.
In
FIG. 4A
, a reference numeral
1
denotes an exposure pattern formed on a photomask, and the exposure pattern
1
is composed of an isolated light shielding film pattern portion
3
, light shielding film pattern portions
5
A,
5
B and
5
C which are densely arranged in parallel with each other.
FIG. 4B
shows a resist pattern
7
that is formed on a surface of a semiconductor wafer by exposing the semiconductor wafer using a photomask including the pattern
1
described and shown in FIG.
4
A. In the resist pattern
7
,
3
A is a resist pattern according to the light shielding film pattern portion
3
,
7
A is a resist pattern according to the light shielding film pattern portion
5
A,
7
B is a resist pattern according to the light shielding film pattern portion
5
B, and
7
C is a resist pattern according to the light shielding film pattern portion
5
C.
As seen from the resist pattern portions
7
A,
7
B and
7
C shown in
FIG. 4B
, individual pattern widths
10
A,
10
B and
10
C of these resist pattern portions are formed narrower than individual widths
9
A,
9
B and
9
C of the light shielding film patterns
5
A,
5
B and
5
C. In other words, there is a problem that these pattern widths
10
A,
10
B and
10
C are formed narrower than the pattern width of the resist pattern
3
A resulting from an influence of the optical proximity effect.
Next, shrinkage of each pattern width shown in FIG.
4
A and
FIG. 4B
resulting from the optical proximity effect is subjected to a light intensity simulation. Based on the simulation result, individual widths
9
A,
9
B and
9
C of the light shielding film patterns
5
A,
5
B and
5
C are corrected, and then, a semiconductor wafer is exposed using the corrected photomask so as to form a resist pattern. The light intensity simulation result of the resist pattern will be described below with reference to FIG.
5
A and FIG.
5
B.
In
FIG. 5A
, a reference numeral
11
denotes an exposure pattern of the corrected photomask, and the exposure pattern
11
is composed of an isolated light shielding film pattern portion
13
, light shielding film pattern portions
15
A,
15
B and
15
C which are densely arranged in parallel with each other.
In the exposure pattern
11
shown in
FIG. 5A
, based on the light intensity simulation result of t

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